OTBN Simulation Results

Tuesday November 04 2025 17:30:07 UTC

GitHub Revision: 80590e0

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke otbn_smoke 18.000s 106.415us 0 1 0.00
V1 single_binary otbn_single 7.000s 37.884us 0 1 0.00
V1 csr_hw_reset otbn_csr_hw_reset 3.000s 46.206us 1 1 100.00
V1 csr_rw otbn_csr_rw 3.000s 50.706us 1 1 100.00
V1 csr_bit_bash otbn_csr_bit_bash 7.000s 117.057us 1 1 100.00
V1 csr_aliasing otbn_csr_aliasing 3.000s 40.978us 1 1 100.00
V1 csr_mem_rw_with_rand_reset otbn_csr_mem_rw_with_rand_reset 7.000s 58.533us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr otbn_csr_rw 3.000s 50.706us 1 1 100.00
otbn_csr_aliasing 3.000s 40.978us 1 1 100.00
V1 mem_walk otbn_mem_walk 20.000s 901.119us 1 1 100.00
V1 mem_partial_access otbn_mem_partial_access 11.000s 247.760us 1 1 100.00
V1 TOTAL 7 9 77.78
V2 reset_recovery otbn_reset 22.000s 782.075us 0 1 0.00
V2 multi_error otbn_multi_err 43.000s 324.289us 0 1 0.00
V2 back_to_back otbn_multi 1.267m 3.268ms 0 1 0.00
V2 stress_all otbn_stress_all 16.000s 105.826us 0 1 0.00
V2 lc_escalation otbn_escalate 6.000s 143.236us 0 1 0.00
V2 zero_state_err_urnd otbn_zero_state_err_urnd 5.000s 41.204us 0 1 0.00
V2 sw_errs_fatal_chk otbn_sw_errs_fatal_chk 6.000s 19.146us 0 1 0.00
V2 alert_test otbn_alert_test 4.000s 54.751us 1 1 100.00
V2 intr_test otbn_intr_test 3.000s 17.119us 1 1 100.00
V2 tl_d_oob_addr_access otbn_tl_errors 3.000s 62.323us 1 1 100.00
V2 tl_d_illegal_access otbn_tl_errors 3.000s 62.323us 1 1 100.00
V2 tl_d_outstanding_access otbn_csr_hw_reset 3.000s 46.206us 1 1 100.00
otbn_csr_rw 3.000s 50.706us 1 1 100.00
otbn_csr_aliasing 3.000s 40.978us 1 1 100.00
otbn_same_csr_outstanding 4.000s 56.873us 1 1 100.00
V2 tl_d_partial_access otbn_csr_hw_reset 3.000s 46.206us 1 1 100.00
otbn_csr_rw 3.000s 50.706us 1 1 100.00
otbn_csr_aliasing 3.000s 40.978us 1 1 100.00
otbn_same_csr_outstanding 4.000s 56.873us 1 1 100.00
V2 TOTAL 4 11 36.36
V2S mem_integrity otbn_imem_err 6.000s 29.439us 1 1 100.00
otbn_dmem_err 6.000s 53.276us 0 1 0.00
V2S internal_integrity otbn_alu_bignum_mod_err 5.000s 19.141us 0 1 0.00
otbn_controller_ispr_rdata_err 9.000s 39.811us 0 1 0.00
otbn_mac_bignum_acc_err 5.000s 55.852us 0 1 0.00
otbn_urnd_err 4.000s 28.938us 1 1 100.00
V2S illegal_bus_access otbn_illegal_mem_acc 6.000s 60.351us 0 1 0.00
V2S otbn_mem_gnt_acc_err otbn_mem_gnt_acc_err 6.000s 21.547us 1 1 100.00
V2S otbn_non_sec_partial_wipe otbn_partial_wipe 4.000s 6.177us 0 1 0.00
V2S tl_intg_err otbn_sec_cm 4.000s 13.459us 0 1 0.00
otbn_tl_intg_err 9.000s 335.574us 1 1 100.00
V2S passthru_mem_tl_intg_err otbn_passthru_mem_tl_intg_err 11.000s 239.256us 1 1 100.00
V2S prim_fsm_check otbn_sec_cm 4.000s 13.459us 0 1 0.00
V2S prim_count_check otbn_sec_cm 4.000s 13.459us 0 1 0.00
V2S sec_cm_mem_scramble otbn_smoke 18.000s 106.415us 0 1 0.00
V2S sec_cm_data_mem_integrity otbn_dmem_err 6.000s 53.276us 0 1 0.00
V2S sec_cm_instruction_mem_integrity otbn_imem_err 6.000s 29.439us 1 1 100.00
V2S sec_cm_bus_integrity otbn_tl_intg_err 9.000s 335.574us 1 1 100.00
V2S sec_cm_controller_fsm_global_esc otbn_escalate 6.000s 143.236us 0 1 0.00
V2S sec_cm_controller_fsm_local_esc otbn_imem_err 6.000s 29.439us 1 1 100.00
otbn_dmem_err 6.000s 53.276us 0 1 0.00
otbn_zero_state_err_urnd 5.000s 41.204us 0 1 0.00
otbn_illegal_mem_acc 6.000s 60.351us 0 1 0.00
otbn_sec_cm 4.000s 13.459us 0 1 0.00
V2S sec_cm_controller_fsm_sparse otbn_sec_cm 4.000s 13.459us 0 1 0.00
V2S sec_cm_scramble_key_sideload otbn_single 7.000s 37.884us 0 1 0.00
V2S sec_cm_scramble_ctrl_fsm_local_esc otbn_imem_err 6.000s 29.439us 1 1 100.00
otbn_dmem_err 6.000s 53.276us 0 1 0.00
otbn_zero_state_err_urnd 5.000s 41.204us 0 1 0.00
otbn_illegal_mem_acc 6.000s 60.351us 0 1 0.00
otbn_sec_cm 4.000s 13.459us 0 1 0.00
V2S sec_cm_scramble_ctrl_fsm_sparse otbn_sec_cm 4.000s 13.459us 0 1 0.00
V2S sec_cm_start_stop_ctrl_fsm_global_esc otbn_escalate 6.000s 143.236us 0 1 0.00
V2S sec_cm_start_stop_ctrl_fsm_local_esc otbn_imem_err 6.000s 29.439us 1 1 100.00
otbn_dmem_err 6.000s 53.276us 0 1 0.00
otbn_zero_state_err_urnd 5.000s 41.204us 0 1 0.00
otbn_illegal_mem_acc 6.000s 60.351us 0 1 0.00
otbn_sec_cm 4.000s 13.459us 0 1 0.00
V2S sec_cm_start_stop_ctrl_fsm_sparse otbn_sec_cm 4.000s 13.459us 0 1 0.00
V2S sec_cm_data_reg_sw_sca otbn_single 7.000s 37.884us 0 1 0.00
V2S sec_cm_ctrl_redun otbn_ctrl_redun 5.000s 38.562us 0 1 0.00
V2S sec_cm_pc_ctrl_flow_redun otbn_pc_ctrl_flow_redun 8.000s 24.035us 1 1 100.00
V2S sec_cm_rnd_bus_consistency otbn_rnd_sec_cm 20.000s 168.707us 0 1 0.00
V2S sec_cm_rnd_rng_digest otbn_rnd_sec_cm 20.000s 168.707us 0 1 0.00
V2S sec_cm_rf_base_data_reg_sw_integrity otbn_rf_base_intg_err 6.000s 68.755us 0 1 0.00
V2S sec_cm_rf_base_data_reg_sw_glitch_detect otbn_sec_cm 4.000s 13.459us 0 1 0.00
V2S sec_cm_stack_wr_ptr_ctr_redun otbn_sec_cm 4.000s 13.459us 0 1 0.00
V2S sec_cm_rf_bignum_data_reg_sw_integrity otbn_rf_bignum_intg_err 11.000s 67.700us 0 1 0.00
V2S sec_cm_rf_bignum_data_reg_sw_glitch_detect otbn_sec_cm 4.000s 13.459us 0 1 0.00
V2S sec_cm_loop_stack_ctr_redun otbn_sec_cm 4.000s 13.459us 0 1 0.00
V2S sec_cm_loop_stack_addr_integrity otbn_stack_addr_integ_chk 6.000s 74.022us 0 1 0.00
V2S sec_cm_call_stack_addr_integrity otbn_stack_addr_integ_chk 6.000s 74.022us 0 1 0.00
V2S sec_cm_start_stop_ctrl_state_consistency otbn_sec_wipe_err 8.000s 77.874us 0 1 0.00
V2S sec_cm_data_mem_sec_wipe otbn_single 7.000s 37.884us 0 1 0.00
V2S sec_cm_instruction_mem_sec_wipe otbn_single 7.000s 37.884us 0 1 0.00
V2S sec_cm_data_reg_sw_sec_wipe otbn_single 7.000s 37.884us 0 1 0.00
V2S sec_cm_write_mem_integrity otbn_multi 1.267m 3.268ms 0 1 0.00
V2S sec_cm_ctrl_flow_count otbn_single 7.000s 37.884us 0 1 0.00
V2S sec_cm_ctrl_flow_sca otbn_single 7.000s 37.884us 0 1 0.00
V2S sec_cm_data_mem_sw_noaccess otbn_sw_no_acc 6.000s 17.772us 0 1 0.00
V2S sec_cm_key_sideload otbn_single 7.000s 37.884us 0 1 0.00
V2S sec_cm_tlul_fifo_ctr_redun otbn_sec_cm 4.000s 13.459us 0 1 0.00
V2S TOTAL 6 20 30.00
V3 stress_all_with_rand_reset otbn_stress_all_with_rand_reset 31.000s 438.212us 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 17 41 41.46

Failure Buckets