PATTGEN Simulation Results

Tuesday November 04 2025 17:30:07 UTC

GitHub Revision: 80590e0

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	1.000s	130.036us	1	1	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	1.000s	48.579us	1	1	100.00
V1	csr_rw	pattgen_csr_rw	2.000s	13.742us	1	1	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	3.000s	768.582us	1	1	100.00
V1	csr_aliasing	pattgen_csr_aliasing	1.000s	65.981us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	1.000s	24.278us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	2.000s	13.742us	1	1	100.00
		pattgen_csr_aliasing	1.000s	65.981us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	perf	pattgen_perf	8.533m	600.000ms	0	1	0.00
V2	cnt_rollover	cnt_rollover	10.000s	4.739ms	1	1	100.00
V2	error	pattgen_error	1.000s	103.499us	1	1	100.00
V2	stress_all	pattgen_stress_all	16.917m	180.693ms	1	1	100.00
V2	alert_test	pattgen_alert_test	2.000s	25.025us	1	1	100.00
V2	intr_test	pattgen_intr_test	1.000s	31.778us	1	1	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	2.000s	116.019us	1	1	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	2.000s	116.019us	1	1	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	1.000s	48.579us	1	1	100.00
		pattgen_csr_rw	2.000s	13.742us	1	1	100.00
		pattgen_csr_aliasing	1.000s	65.981us	1	1	100.00
		pattgen_same_csr_outstanding	1.000s	25.612us	1	1	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	1.000s	48.579us	1	1	100.00
		pattgen_csr_rw	2.000s	13.742us	1	1	100.00
		pattgen_csr_aliasing	1.000s	65.981us	1	1	100.00
		pattgen_same_csr_outstanding	1.000s	25.612us	1	1	100.00
V2		TOTAL			7	8	87.50
V2S	tl_intg_err	pattgen_tl_intg_err	2.000s	94.391us	1	1	100.00
		pattgen_sec_cm	2.000s	183.432us	1	1	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	2.000s	94.391us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	14.000s	1.290ms	1	1	100.00
V3		TOTAL			1	1	100.00
	Unmapped tests	pattgen_inactive_level	3.417m	10.004ms	0	1	0.00
		TOTAL			16	18	88.89

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test pattgen_perf has 1 failures.

    • 0.pattgen_perf.93796006383657442208637728703159159085416502129335582767582401612600770683146
      Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_perf/latest/run.log

        UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) has 1 failures:

  • Test pattgen_inactive_level has 1 failures.

    • 0.pattgen_inactive_level.49745746507950148051150284025758668553580199527666113674412632405702160802818
      Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_inactive_level/latest/run.log

        UVM_FATAL @ 10003730957 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x439dcc50, Comparison=CompareOpEq, exp_data=0x0, call_count=9)
        UVM_INFO @ 10003730957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---