ROM_CTRL/32KB Simulation Results

Tuesday November 04 2025 17:30:07 UTC

GitHub Revision: 80590e0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 4.710s 562.739us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 4.670s 133.460us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 4.290s 167.360us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 3.560s 371.460us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 5.850s 1.063ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 3.420s 1.845ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 4.290s 167.360us 1 1 100.00
rom_ctrl_csr_aliasing 5.850s 1.063ms 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 4.480s 170.548us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 3.430s 326.929us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 5.280s 569.783us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 20.250s 4.381ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 6.660s 842.117us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 3.840s 288.092us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 6.080s 579.024us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 6.080s 579.024us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 4.670s 133.460us 1 1 100.00
rom_ctrl_csr_rw 4.290s 167.360us 1 1 100.00
rom_ctrl_csr_aliasing 5.850s 1.063ms 1 1 100.00
rom_ctrl_same_csr_outstanding 3.720s 126.867us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 4.670s 133.460us 1 1 100.00
rom_ctrl_csr_rw 4.290s 167.360us 1 1 100.00
rom_ctrl_csr_aliasing 5.850s 1.063ms 1 1 100.00
rom_ctrl_same_csr_outstanding 3.720s 126.867us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 1.252m 2.858ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 12.750s 467.509us 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 3.259m 1.593ms 1 1 100.00
rom_ctrl_tl_intg_err 23.230s 2.550ms 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 3.259m 1.593ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 3.259m 1.593ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.252m 2.858ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.252m 2.858ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.252m 2.858ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.252m 2.858ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.252m 2.858ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 3.259m 1.593ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 3.259m 1.593ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 4.710s 562.739us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 4.710s 562.739us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 4.710s 562.739us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 23.230s 2.550ms 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.252m 2.858ms 1 1 100.00
rom_ctrl_kmac_err_chk 6.660s 842.117us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 1.252m 2.858ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 1.252m 2.858ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 1.252m 2.858ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 12.750s 467.509us 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 3.259m 1.593ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 2.443m 10.508ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00