RV_DM/USE_JTAG_INTERFACE Simulation Results

Tuesday November 04 2025 17:30:07 UTC

GitHub Revision: `80590e0`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rv_dm_smoke	1.310s	1.407ms	1	1	100.00
V1	jtag_dtm_csr_hw_reset	rv_dm_jtag_dtm_csr_hw_reset	1.070s	737.121us	1	1	100.00
V1	jtag_dtm_csr_rw	rv_dm_jtag_dtm_csr_rw	1.510s	441.814us	1	1	100.00
V1	jtag_dtm_csr_bit_bash	rv_dm_jtag_dtm_csr_bit_bash	34.360s	16.259ms	1	1	100.00
V1	jtag_dtm_csr_aliasing	rv_dm_jtag_dtm_csr_aliasing	3.070s	2.318ms	1	1	100.00
V1	jtag_dmi_csr_hw_reset	rv_dm_jtag_dmi_csr_hw_reset	5.780s	7.246ms	1	1	100.00
V1	jtag_dmi_csr_rw	rv_dm_jtag_dmi_csr_rw	1.520s	1.139ms	1	1	100.00
V1	jtag_dmi_csr_bit_bash	rv_dm_jtag_dmi_csr_bit_bash	2.123m	83.256ms	1	1	100.00
V1	jtag_dmi_csr_aliasing	rv_dm_jtag_dmi_csr_aliasing	31.460s	29.640ms	1	1	100.00
V1	jtag_dmi_cmderr_busy	rv_dm_cmderr_busy	1.000s	485.754us	1	1	100.00
V1	jtag_dmi_cmderr_not_supported	rv_dm_cmderr_not_supported	1.130s	210.874us	1	1	100.00
V1	cmderr_exception	rv_dm_cmderr_exception	0.800s	252.235us	1	1	100.00
V1	mem_tl_access_resuming	rv_dm_mem_tl_access_resuming	0.990s	175.218us	1	1	100.00
V1	mem_tl_access_halted	rv_dm_mem_tl_access_halted	0.960s	154.697us	1	1	100.00
V1	cmderr_halt_resume	rv_dm_cmderr_halt_resume	0.790s	153.156us	1	1	100.00
V1	dataaddr_rw_access	rv_dm_dataaddr_rw_access	0.820s	145.266us	1	1	100.00
V1	halt_resume	rv_dm_halt_resume_whereto	0.830s	318.735us	1	1	100.00
V1	progbuf_busy	rv_dm_cmderr_busy	1.000s	485.754us	1	1	100.00
V1	abstractcmd_status	rv_dm_abstractcmd_status	0.750s	152.580us	1	1	100.00
V1	progbuf_read_write_execute	rv_dm_progbuf_read_write_execute	1.950s	1.011ms	1	1	100.00
V1	progbuf_exception	rv_dm_cmderr_exception	0.800s	252.235us	1	1	100.00
V1	rom_read_access	rv_dm_rom_read_access	1.010s	128.173us	1	1	100.00
V1	csr_hw_reset	rv_dm_csr_hw_reset	1.680s	290.863us	1	1	100.00
V1	csr_rw	rv_dm_csr_rw	1.460s	129.759us	1	1	100.00
V1	csr_bit_bash	rv_dm_csr_bit_bash	38.960s	1.899ms	1	1	100.00
V1	csr_aliasing	rv_dm_csr_aliasing	43.530s	4.488ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_dm_csr_mem_rw_with_rand_reset	1.860s	193.664us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_dm_csr_aliasing	43.530s	4.488ms	1	1	100.00
		rv_dm_csr_rw	1.460s	129.759us	1	1	100.00
V1	mem_walk	rv_dm_mem_walk	0.850s	61.088us	1	1	100.00
V1	mem_partial_access	rv_dm_mem_partial_access	0.880s	46.116us	1	1	100.00
V1		TOTAL			27	27	100.00
V2	idcode	rv_dm_smoke	1.310s	1.407ms	1	1	100.00
V2	jtag_dtm_hard_reset	rv_dm_jtag_dtm_hard_reset	1.010s	850.914us	1	1	100.00
V2	jtag_dtm_idle_hint	rv_dm_jtag_dtm_idle_hint	1.040s	126.621us	1	1	100.00
V2	jtag_dmi_failed_op	rv_dm_dmi_failed_op	0.960s	86.157us	1	1	100.00
V2	jtag_dmi_dm_inactive	rv_dm_jtag_dmi_dm_inactive	1.110s	350.009us	1	1	100.00
V2	sba	rv_dm_sba_tl_access	4.615m	300.000ms	0	1	0.00
		rv_dm_delayed_resp_sba_tl_access	4.204m	300.000ms	0	1	0.00
V2	bad_sba	rv_dm_bad_sba_tl_access	7.941m	300.000ms	0	1	0.00
V2	sba_autoincrement	rv_dm_autoincr_sba_tl_access	3.616m	300.000ms	0	1	0.00
V2	jtag_dmi_debug_disabled	rv_dm_jtag_dmi_debug_disabled	1.640s	535.902us	1	1	100.00
V2	sba_debug_disabled	rv_dm_sba_debug_disabled	3.550s	3.171ms	1	1	100.00
V2	ndmreset_req	rv_dm_ndmreset_req	1.140s	153.160us	1	1	100.00
V2	hart_unavail	rv_dm_hart_unavail	0.690s	247.829us	1	1	100.00
V2	tap_ctrl_transitions	rv_dm_tap_fsm	5.490s	9.300ms	1	1	100.00
		rv_dm_tap_fsm_rand_reset	0.710s	21.239us	0	1	0.00
V2	hartsel_warl	rv_dm_hartsel_warl	0.860s	54.840us	1	1	100.00
V2	stress_all	rv_dm_stress_all	2.200s	2.119ms	1	1	100.00
V2	alert_test	rv_dm_alert_test	0.830s	34.078us	1	1	100.00
V2	tl_d_oob_addr_access	rv_dm_tl_errors	0.740s	56.842us	0	1	0.00
V2	tl_d_illegal_access	rv_dm_tl_errors	0.740s	56.842us	0	1	0.00
V2	tl_d_outstanding_access	rv_dm_csr_aliasing	43.530s	4.488ms	1	1	100.00
		rv_dm_csr_hw_reset	1.680s	290.863us	1	1	100.00
		rv_dm_csr_rw	1.460s	129.759us	1	1	100.00
		rv_dm_same_csr_outstanding	3.250s	369.367us	1	1	100.00
V2	tl_d_partial_access	rv_dm_csr_aliasing	43.530s	4.488ms	1	1	100.00
		rv_dm_csr_hw_reset	1.680s	290.863us	1	1	100.00
		rv_dm_csr_rw	1.460s	129.759us	1	1	100.00
		rv_dm_same_csr_outstanding	3.250s	369.367us	1	1	100.00
V2		TOTAL			13	19	68.42
V2S	tl_intg_err	rv_dm_sec_cm	1.080s	1.063ms	1	1	100.00
		rv_dm_tl_intg_err	8.250s	1.614ms	1	1	100.00
V2S	sec_cm_bus_integrity	rv_dm_tl_intg_err	8.250s	1.614ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	rv_dm_sba_debug_disabled	3.550s	3.171ms	1	1	100.00
		rv_dm_debug_disabled	0.930s	57.687us	1	1	100.00
V2S	sec_cm_lc_dft_en_intersig_mubi	rv_dm_sba_debug_disabled	3.550s	3.171ms	1	1	100.00
		rv_dm_debug_disabled	0.930s	57.687us	1	1	100.00
V2S	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi	rv_dm_smoke	1.310s	1.407ms	1	1	100.00
V2S	sec_cm_dm_en_ctrl_lc_gated	rv_dm_buffered_enable	1.300s	334.152us	1	1	100.00
V2S	sec_cm_sba_tl_lc_gate_fsm_sparse	rv_dm_sparse_lc_gate_fsm	0.740s	108.186us	1	1	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	rv_dm_sparse_lc_gate_fsm	0.740s	108.186us	1	1	100.00
V2S	sec_cm_exec_ctrl_mubi	rv_dm_buffered_enable	1.300s	334.152us	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	rv_dm_stress_all_with_rand_reset	0.840s	26.448us	0	1	0.00
V3		TOTAL			0	1	0.00
	Unmapped tests	rv_dm_scanmode	0.760s	22.939us	1	1	100.00
		TOTAL			46	53	86.79

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:
- Test rv_dm_sba_tl_access has 1 failures.
  - 0.rv_dm_sba_tl_access.62903232010855571135686476875961250834403460505247325780407964864567894701645
    Line 83, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_sba_tl_access/latest/run.log
```
  UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rv_dm_delayed_resp_sba_tl_access has 1 failures.
  - 0.rv_dm_delayed_resp_sba_tl_access.59677684134057077805781853223808426428692931247716455660765887344509731734268
    Line 83, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_delayed_resp_sba_tl_access/latest/run.log
```
  UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rv_dm_bad_sba_tl_access has 1 failures.
  - 0.rv_dm_bad_sba_tl_access.41632026243981120377334062984348184176213510587809587588360477454817208297839
    Line 83, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_bad_sba_tl_access/latest/run.log
```
  UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rv_dm_autoincr_sba_tl_access has 1 failures.
  - 0.rv_dm_autoincr_sba_tl_access.54166018430021252093344637525818568913649888072982038453069777512246268961991
    Line 83, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_autoincr_sba_tl_access/latest/run.log
```
  UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@6116) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test rv_dm_tap_fsm_rand_reset has 1 failures.

0.rv_dm_tap_fsm_rand_reset.31202411985596235659709375283124666821281182335701932541746742742981047547325
Line 76, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_tap_fsm_rand_reset/latest/run.log

  UVM_ERROR @  21238507 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@6116) { a_addr: 'ha5bc95c0  a_data: 'ha7afeba1  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hdd  a_opcode: 'h4  a_user: 'h1858b  d_param: 'h0  d_source: 'hdd  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @  21238507 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@5778) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test rv_dm_stress_all_with_rand_reset has 1 failures.

0.rv_dm_stress_all_with_rand_reset.103239936769552204831874434744626355645101815400069712461194410832669764948998
Line 76, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  26447988 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@5778) { a_addr: 'h4b02a478  a_data: 'hd789cd55  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hff  a_opcode: 'h4  a_user: 'h1ae16  d_param: 'h0  d_source: 'hff  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @  26447988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@5656) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test rv_dm_tl_errors has 1 failures.

0.rv_dm_tl_errors.8487738518523431581798176138326797349015134713429080041531736546575076618365
Line 75, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_tl_errors/latest/run.log

  UVM_ERROR @  56842483 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@5656) { a_addr: 'hf8b9e748  a_data: 'h433aa228  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h48  a_opcode: 'h4  a_user: 'h188c9  d_param: 'h0  d_source: 'h48  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @  56842483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---