RV_TIMER Simulation Results

Tuesday November 04 2025 17:30:07 UTC

GitHub Revision: 80590e0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	0.940s	317.992us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.680s	42.805us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	0.810s	12.451us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	2.150s	233.066us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.100s	37.001us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.060s	151.701us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.810s	12.451us	1	1	100.00
		rv_timer_csr_aliasing	1.100s	37.001us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	0.880s	1.333ms	0	1	0.00
V2	disabled	rv_timer_disabled	3.220s	2.128ms	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	1.580m	95.453ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	1.580m	95.453ms	1	1	100.00
V2	stress	rv_timer_stress_all	6.130s	5.364ms	1	1	100.00
V2	alert_test	rv_timer_alert_test	0.730s	45.646us	1	1	100.00
V2	intr_test	rv_timer_intr_test	0.580s	35.230us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	1.350s	454.268us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	1.350s	454.268us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.680s	42.805us	1	1	100.00
		rv_timer_csr_rw	0.810s	12.451us	1	1	100.00
		rv_timer_csr_aliasing	1.100s	37.001us	1	1	100.00
		rv_timer_same_csr_outstanding	0.910s	127.614us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.680s	42.805us	1	1	100.00
		rv_timer_csr_rw	0.810s	12.451us	1	1	100.00
		rv_timer_csr_aliasing	1.100s	37.001us	1	1	100.00
		rv_timer_same_csr_outstanding	0.910s	127.614us	1	1	100.00
V2		TOTAL			7	8	87.50
V2S	tl_intg_err	rv_timer_sec_cm	0.940s	39.331us	1	1	100.00
		rv_timer_tl_intg_err	1.120s	176.672us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.120s	176.672us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	min_value	rv_timer_min	1.150s	672.468us	0	1	0.00
V3	max_value	rv_timer_max	0.740s	29.033us	1	1	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	3.260s	625.384us	1	1	100.00
V3		TOTAL			2	3	66.67
		TOTAL			17	19	89.47

Failure Buckets

• UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 2 failures:

  • Test rv_timer_min has 1 failures.

    • 0.rv_timer_min.30926754762535185330809846423147950435523016121859667346438987817250694096543
      Line 73, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_min/latest/run.log

        UVM_FATAL @ 672468422 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x5e217d04) == 0x1
        UVM_INFO @ 672468422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rv_timer_random_reset has 1 failures.

    • 0.rv_timer_random_reset.110571901626062887472415163301015051204899402356248457318592219760976054171047
      Line 73, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log

        UVM_FATAL @ 1333013732 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xd5a1a104) == 0x1
        UVM_INFO @ 1333013732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---