SPI_DEVICE/1R1W Simulation Results

Tuesday November 04 2025 17:30:07 UTC

GitHub Revision: 80590e0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	2.955m	69.746ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.080s	22.832us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.700s	35.981us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	24.810s	9.739ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	14.410s	624.761us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.070s	97.409us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.700s	35.981us	1	1	100.00
		spi_device_csr_aliasing	14.410s	624.761us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.650s	11.079us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.440s	96.216us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.080s	87.870us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	0.840s	1.034us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	0.680s	3.637us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	1.800s	168.900us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.800s	168.900us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	4.320s	6.673ms	1	1	100.00
		spi_device_tpm_sts_read	0.900s	24.126us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	18.850s	9.730ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	2.650s	2.545ms	1	1	100.00
		spi_device_flash_all	39.090s	117.799ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	8.060s	19.320ms	1	1	100.00
		spi_device_flash_all	39.090s	117.799ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	8.060s	19.320ms	1	1	100.00
		spi_device_flash_all	39.090s	117.799ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	39.090s	117.799ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	2.770s	402.296us	1	1	100.00
		spi_device_flash_all	39.090s	117.799ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	2.770s	402.296us	1	1	100.00
		spi_device_flash_all	39.090s	117.799ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	2.770s	402.296us	1	1	100.00
		spi_device_flash_all	39.090s	117.799ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	2.770s	402.296us	1	1	100.00
		spi_device_flash_all	39.090s	117.799ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	2.770s	402.296us	1	1	100.00
		spi_device_flash_all	39.090s	117.799ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	6.950s	10.955ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	2.620s	664.949us	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.620s	664.949us	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.620s	664.949us	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	3.820s	458.460us	1	1	100.00
		spi_device_read_buffer_direct	6.380s	5.386ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.620s	664.949us	1	1	100.00
		spi_device_flash_all	39.090s	117.799ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	39.090s	117.799ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	39.090s	117.799ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	6.480s	772.904us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	6.480s	772.904us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	2.955m	69.746ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	46.030s	27.828ms	1	1	100.00
V2	stress_all	spi_device_stress_all	6.958m	136.697ms	1	1	100.00
V2	alert_test	spi_device_alert_test	0.930s	11.688us	1	1	100.00
V2	intr_test	spi_device_intr_test	0.870s	16.993us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	3.360s	246.481us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	3.360s	246.481us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.080s	22.832us	1	1	100.00
		spi_device_csr_rw	1.700s	35.981us	1	1	100.00
		spi_device_csr_aliasing	14.410s	624.761us	1	1	100.00
		spi_device_same_csr_outstanding	2.360s	162.169us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.080s	22.832us	1	1	100.00
		spi_device_csr_rw	1.700s	35.981us	1	1	100.00
		spi_device_csr_aliasing	14.410s	624.761us	1	1	100.00
		spi_device_same_csr_outstanding	2.360s	162.169us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.500s	202.839us	1	1	100.00
		spi_device_tl_intg_err	6.170s	1.059ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	6.170s	1.059ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	36.470s	11.458ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.88113167725163699518373622190628542363939089823474561150609817683648449022072
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @    727954 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[22])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @    727954 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @    727954 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[918])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.7767854974660110130983283375673095383232281474649269999619594569252582843411
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   1094586 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xeca8b6 [111011001010100010110110] vs 0x0 [0])
        UVM_ERROR @   1136586 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x32f98f [1100101111100110001111] vs 0x0 [0])
        UVM_ERROR @   1137586 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x6f9496 [11011111001010010010110] vs 0x0 [0])
        UVM_ERROR @   1207586 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x267364 [1001100111001101100100] vs 0x0 [0])
        UVM_ERROR @   1260586 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x107978 [100000111100101111000] vs 0x0 [0])