SPI_DEVICE/2P Simulation Results

Tuesday November 04 2025 17:30:07 UTC

GitHub Revision: 80590e0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	1.623m	7.549ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.230s	49.118us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.090s	173.896us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	9.300s	703.819us	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	9.890s	215.991us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.710s	149.773us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.090s	173.896us	1	1	100.00
		spi_device_csr_aliasing	9.890s	215.991us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.660s	31.108us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.470s	84.492us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	0.800s	36.733us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.020s	58.865us	1	1	100.00
V2	mem_cfg	spi_device_ram_cfg	0.940s	43.289us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	2.430s	356.997us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	2.430s	356.997us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	4.050s	3.705ms	1	1	100.00
		spi_device_tpm_sts_read	1.040s	253.896us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	8.430s	3.568ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	8.020s	20.650ms	1	1	100.00
		spi_device_flash_all	22.330s	22.828ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	4.150s	7.207ms	1	1	100.00
		spi_device_flash_all	22.330s	22.828ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	4.150s	7.207ms	1	1	100.00
		spi_device_flash_all	22.330s	22.828ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	22.330s	22.828ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	8.310s	1.495ms	1	1	100.00
		spi_device_flash_all	22.330s	22.828ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	8.310s	1.495ms	1	1	100.00
		spi_device_flash_all	22.330s	22.828ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	8.310s	1.495ms	1	1	100.00
		spi_device_flash_all	22.330s	22.828ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	8.310s	1.495ms	1	1	100.00
		spi_device_flash_all	22.330s	22.828ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	8.310s	1.495ms	1	1	100.00
		spi_device_flash_all	22.330s	22.828ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	6.600s	1.140ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	19.860s	9.064ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	19.860s	9.064ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	19.860s	9.064ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	2.060s	68.137us	1	1	100.00
		spi_device_read_buffer_direct	2.890s	120.835us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	19.860s	9.064ms	1	1	100.00
		spi_device_flash_all	22.330s	22.828ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	22.330s	22.828ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	22.330s	22.828ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	2.580s	41.146us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	2.580s	41.146us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	1.623m	7.549ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	7.002m	69.908ms	1	1	100.00
V2	stress_all	spi_device_stress_all	6.652m	67.760ms	1	1	100.00
V2	alert_test	spi_device_alert_test	0.970s	14.492us	1	1	100.00
V2	intr_test	spi_device_intr_test	0.930s	25.271us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	3.320s	62.910us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	3.320s	62.910us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.230s	49.118us	1	1	100.00
		spi_device_csr_rw	2.090s	173.896us	1	1	100.00
		spi_device_csr_aliasing	9.890s	215.991us	1	1	100.00
		spi_device_same_csr_outstanding	2.360s	314.213us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.230s	49.118us	1	1	100.00
		spi_device_csr_rw	2.090s	173.896us	1	1	100.00
		spi_device_csr_aliasing	9.890s	215.991us	1	1	100.00
		spi_device_same_csr_outstanding	2.360s	314.213us	1	1	100.00
V2		TOTAL			22	22	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.400s	171.868us	1	1	100.00
		spi_device_tl_intg_err	8.950s	778.406us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	8.950s	778.406us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	0.900s	203.481us	1	1	100.00
		TOTAL			33	33	100.00