SPI_HOST Simulation Results

Tuesday November 04 2025 17:30:07 UTC

GitHub Revision: 80590e0

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	9.000s	34.243us	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	1.000s	19.937us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	2.000s	19.316us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	3.000s	1.152ms	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	2.000s	35.037us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	2.000s	31.377us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	2.000s	19.316us	1	1	100.00
		spi_host_csr_aliasing	2.000s	35.037us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	1.000s	38.196us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	1.000s	24.966us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	2.000s	146.506us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	3.000s	467.749us	1	1	100.00
		spi_host_error_cmd	1.000s	19.466us	1	1	100.00
		spi_host_event	54.000s	8.025ms	1	1	100.00
V2	clock_rate	spi_host_speed	2.000s	133.920us	1	1	100.00
V2	speed	spi_host_speed	2.000s	133.920us	1	1	100.00
V2	chip_select_timing	spi_host_speed	2.000s	133.920us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	6.000s	238.769us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	2.000s	23.529us	1	1	100.00
V2	cpol_cpha	spi_host_speed	2.000s	133.920us	1	1	100.00
V2	full_cycle	spi_host_speed	2.000s	133.920us	1	1	100.00
V2	duplex	spi_host_smoke	9.000s	34.243us	1	1	100.00
V2	tx_rx_only	spi_host_smoke	9.000s	34.243us	1	1	100.00
V2	stress_all	spi_host_stress_all	5.000s	153.339us	1	1	100.00
V2	spien	spi_host_spien	7.000s	835.310us	1	1	100.00
V2	stall	spi_host_status_stall	46.000s	31.311ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	2.000s	137.011us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	3.000s	467.749us	1	1	100.00
V2	alert_test	spi_host_alert_test	1.000s	16.434us	1	1	100.00
V2	intr_test	spi_host_intr_test	2.000s	25.885us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	2.000s	165.973us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	2.000s	165.973us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	1.000s	19.937us	1	1	100.00
		spi_host_csr_rw	2.000s	19.316us	1	1	100.00
		spi_host_csr_aliasing	2.000s	35.037us	1	1	100.00
		spi_host_same_csr_outstanding	1.000s	46.704us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	1.000s	19.937us	1	1	100.00
		spi_host_csr_rw	2.000s	19.316us	1	1	100.00
		spi_host_csr_aliasing	2.000s	35.037us	1	1	100.00
		spi_host_same_csr_outstanding	1.000s	46.704us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	2.000s	206.714us	1	1	100.00
		spi_host_sec_cm	1.000s	176.870us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	2.000s	206.714us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	1.933m	200.000ms	0	1	0.00
		TOTAL			25	26	96.15

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test spi_host_upper_range_clkdiv has 1 failures.

    • 0.spi_host_upper_range_clkdiv.65884196413159640421490224353001890230567380829923592294325329596264079657444
      Line 159, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/0.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---