SRAM_CTRL/MAIN Simulation Results

Tuesday November 04 2025 17:30:07 UTC

GitHub Revision: 80590e0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 15.690s 5.581ms 1 1 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.760s 99.243us 1 1 100.00
V1 csr_rw sram_ctrl_csr_rw 0.890s 33.513us 1 1 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 2.000s 747.448us 1 1 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.860s 19.278us 1 1 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 2.670s 735.162us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.890s 33.513us 1 1 100.00
sram_ctrl_csr_aliasing 0.860s 19.278us 1 1 100.00
V1 mem_walk sram_ctrl_mem_walk 1.935m 57.789ms 1 1 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 57.280s 1.392ms 1 1 100.00
V1 TOTAL 8 8 100.00
V2 multiple_keys sram_ctrl_multiple_keys 7.438m 29.264ms 1 1 100.00
V2 stress_pipeline sram_ctrl_stress_pipeline 3.531m 4.999ms 1 1 100.00
V2 bijection sram_ctrl_bijection 15.505m 212.508ms 1 1 100.00
V2 access_during_key_req sram_ctrl_access_during_key_req 12.815m 81.148ms 1 1 100.00
V2 lc_escalation sram_ctrl_lc_escalation 31.500s 8.948ms 1 1 100.00
V2 executable sram_ctrl_executable 8.813m 60.936ms 1 1 100.00
V2 partial_access sram_ctrl_partial_access 5.730s 747.953us 1 1 100.00
sram_ctrl_partial_access_b2b 3.851m 25.939ms 1 1 100.00
V2 max_throughput sram_ctrl_max_throughput 14.250s 2.621ms 1 1 100.00
sram_ctrl_throughput_w_partial_write 1.066m 2.515ms 1 1 100.00
sram_ctrl_throughput_w_readback 5.610s 5.605ms 1 1 100.00
V2 regwen sram_ctrl_regwen 1.423m 5.863ms 1 1 100.00
V2 ram_cfg sram_ctrl_ram_cfg 3.680s 352.791us 1 1 100.00
V2 stress_all sram_ctrl_stress_all 1.242h 150.058ms 1 1 100.00
V2 alert_test sram_ctrl_alert_test 0.750s 37.360us 1 1 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 2.170s 279.585us 1 1 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 2.170s 279.585us 1 1 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.760s 99.243us 1 1 100.00
sram_ctrl_csr_rw 0.890s 33.513us 1 1 100.00
sram_ctrl_csr_aliasing 0.860s 19.278us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.700s 38.205us 1 1 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.760s 99.243us 1 1 100.00
sram_ctrl_csr_rw 0.890s 33.513us 1 1 100.00
sram_ctrl_csr_aliasing 0.860s 19.278us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.700s 38.205us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 18.440s 3.829ms 1 1 100.00
V2S tl_intg_err sram_ctrl_sec_cm 0.940s 1.259us 0 1 0.00
sram_ctrl_tl_intg_err 1.490s 1.490ms 1 1 100.00
V2S prim_count_check sram_ctrl_sec_cm 0.940s 1.259us 0 1 0.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 1.490s 1.490ms 1 1 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 1.423m 5.863ms 1 1 100.00
V2S sec_cm_readback_config_regwen sram_ctrl_regwen 1.423m 5.863ms 1 1 100.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.890s 33.513us 1 1 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 8.813m 60.936ms 1 1 100.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 8.813m 60.936ms 1 1 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 8.813m 60.936ms 1 1 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 31.500s 8.948ms 1 1 100.00
V2S sec_cm_prim_ram_ctrl_mubi sram_ctrl_mubi_enc_err 5.760s 2.990ms 0 1 0.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 18.440s 3.829ms 1 1 100.00
V2S sec_cm_mem_readback sram_ctrl_readback_err 7.380s 846.339us 0 1 0.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 15.690s 5.581ms 1 1 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 15.690s 5.581ms 1 1 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 8.813m 60.936ms 1 1 100.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 0.940s 1.259us 0 1 0.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 31.500s 8.948ms 1 1 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 0.940s 1.259us 0 1 0.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 0.940s 1.259us 0 1 0.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 15.690s 5.581ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 0.940s 1.259us 0 1 0.00
V2S TOTAL 2 5 40.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 31.040s 3.354ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 28 31 90.32

Failure Buckets