SRAM_CTRL/RET Simulation Results

Tuesday November 04 2025 17:30:07 UTC

GitHub Revision: 80590e0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	52.540s	611.684us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.980s	48.427us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.660s	12.562us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.840s	246.450us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.830s	46.020us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	1.650s	586.247us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.660s	12.562us	1	1	100.00
		sram_ctrl_csr_aliasing	0.830s	46.020us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	7.900s	523.317us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.200s	353.096us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	4.408m	9.792ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.717m	6.375ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	28.840s	1.873ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	1.522m	5.193ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	4.340s	874.879us	1	1	100.00
V2	executable	sram_ctrl_executable	8.856m	48.678ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	48.340s	1.912ms	1	1	100.00
		sram_ctrl_partial_access_b2b	3.910m	26.569ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	45.060s	228.720us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	28.270s	453.688us	1	1	100.00
		sram_ctrl_throughput_w_readback	1.970s	47.802us	1	1	100.00
V2	regwen	sram_ctrl_regwen	12.527m	116.142ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.050s	85.605us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	1.212h	284.878ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.740s	11.245us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.320s	825.999us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.320s	825.999us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.980s	48.427us	1	1	100.00
		sram_ctrl_csr_rw	0.660s	12.562us	1	1	100.00
		sram_ctrl_csr_aliasing	0.830s	46.020us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.990s	25.068us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.980s	48.427us	1	1	100.00
		sram_ctrl_csr_rw	0.660s	12.562us	1	1	100.00
		sram_ctrl_csr_aliasing	0.830s	46.020us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.990s	25.068us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.620s	411.288us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.880s	3.903us	0	1	0.00
		sram_ctrl_tl_intg_err	1.530s	174.264us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.880s	3.903us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.530s	174.264us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	12.527m	116.142ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	12.527m	116.142ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.660s	12.562us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	8.856m	48.678ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	8.856m	48.678ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	8.856m	48.678ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	4.340s	874.879us	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.010s	127.444us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.620s	411.288us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	0.900s	28.470us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	52.540s	611.684us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	52.540s	611.684us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	8.856m	48.678ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.880s	3.903us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	4.340s	874.879us	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.880s	3.903us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.880s	3.903us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	52.540s	611.684us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.880s	3.903us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	2.750m	3.366ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.26027590317462497633418278183609507397433011833166132045997831715952450372849
      Line 98, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.tlul_assert_device_ram.gen_device.gen_d2h.respMustHaveReq_A: started at 2412664ps failed at 2412664ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        UVM_ERROR @   3902664 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   3902664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]