UART Simulation Results

Tuesday November 04 2025 17:30:07 UTC

GitHub Revision: 80590e0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	2.350s	424.121us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.810s	15.122us	1	1	100.00
V1	csr_rw	uart_csr_rw	0.690s	14.129us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.280s	125.880us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	0.700s	31.107us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	0.810s	23.893us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.690s	14.129us	1	1	100.00
		uart_csr_aliasing	0.700s	31.107us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	31.990s	66.310ms	1	1	100.00
V2	parity	uart_smoke	2.350s	424.121us	1	1	100.00
		uart_tx_rx	31.990s	66.310ms	1	1	100.00
V2	parity_error	uart_intr	4.570s	11.188ms	1	1	100.00
		uart_rx_parity_err	21.840s	58.677ms	1	1	100.00
V2	watermark	uart_tx_rx	31.990s	66.310ms	1	1	100.00
		uart_intr	4.570s	11.188ms	1	1	100.00
V2	fifo_full	uart_fifo_full	19.760s	34.588ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	33.970s	112.077ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	40.030s	32.992ms	1	1	100.00
V2	rx_frame_err	uart_intr	4.570s	11.188ms	1	1	100.00
V2	rx_break_err	uart_intr	4.570s	11.188ms	1	1	100.00
V2	rx_timeout	uart_intr	4.570s	11.188ms	1	1	100.00
V2	perf	uart_perf	11.213m	19.959ms	0	1	0.00
V2	sys_loopback	uart_loopback	2.880s	10.731ms	1	1	100.00
V2	line_loopback	uart_loopback	2.880s	10.731ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	7.790s	10.711ms	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	4.020s	5.345ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	3.440s	923.909us	1	1	100.00
V2	rx_oversample	uart_rx_oversample	2.230s	1.375ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	4.981m	59.468ms	1	1	100.00
V2	stress_all	uart_stress_all	25.090s	76.653ms	1	1	100.00
V2	alert_test	uart_alert_test	0.570s	45.080us	1	1	100.00
V2	intr_test	uart_intr_test	0.600s	20.858us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.410s	107.978us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.410s	107.978us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.810s	15.122us	1	1	100.00
		uart_csr_rw	0.690s	14.129us	1	1	100.00
		uart_csr_aliasing	0.700s	31.107us	1	1	100.00
		uart_same_csr_outstanding	0.800s	196.693us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.810s	15.122us	1	1	100.00
		uart_csr_rw	0.690s	14.129us	1	1	100.00
		uart_csr_aliasing	0.700s	31.107us	1	1	100.00
		uart_same_csr_outstanding	0.800s	196.693us	1	1	100.00
V2		TOTAL			16	18	88.89
V2S	tl_intg_err	uart_sec_cm	0.890s	110.084us	1	1	100.00
		uart_tl_intg_err	1.330s	137.758us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.330s	137.758us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	13.600s	1.396ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			25	27	92.59

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * has 1 failures:

  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.99995084292246338577970638784407638029373725334568319981495735360414718859250
      Line 78, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @ 9738713738 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 6,                                 clk_pulses: 0
        UVM_ERROR @ 9738734146 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 9738754554 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4 [0x4] vs 255 [0xff]) reg name: uart_reg_block.rdata
        UVM_ERROR @ 9738774962 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 9738795370 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4 [0x4] vs 255 [0xff]) reg name: uart_reg_block.rdata
      

• UVM_ERROR (uart_scoreboard.sv:447) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: TxEmpty has 1 failures:

  • Test uart_perf has 1 failures.

    • 0.uart_perf.87869711036868798315666597924732677387712187712261886141111485823654127073229
      Line 71, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_perf/latest/run.log

        UVM_ERROR @   1685898 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
        UVM_INFO @ 1449950256 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 1/9
        UVM_INFO @ 1604549836 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 2/9
        UVM_INFO @ 4028297501 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 3/9
        UVM_INFO @ 6216826038 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 4/9