CHIP Simulation Results

Tuesday November 04 2025 17:30:07 UTC

GitHub Revision: `80590e0`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	1.967m	2.418ms	1	1	100.00
		chip_sw_example_rom	58.000s	2.368ms	1	1	100.00
		chip_sw_example_manufacturer	1.869m	2.506ms	1	1	100.00
		chip_sw_example_concurrency	2.552m	2.795ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	3.998m	6.222ms	1	1	100.00
V1	csr_rw	chip_csr_rw	5.778m	6.351ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	6.301m	5.834ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	52.750m	29.985ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	1.077m	2.172ms	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	52.750m	29.985ms	1	1	100.00
		chip_csr_rw	5.778m	6.351ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	5.890s	189.363us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	4.246m	4.140ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	4.246m	4.140ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	4.246m	4.140ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	5.515m	4.791ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	5.515m	4.791ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	6.684m	4.352ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	6.012m	4.377ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	6.377m	4.678ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	30.029m	14.002ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	6.077m	4.291ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	5.660m	4.617ms	1	1	100.00
V1		TOTAL			17	18	94.44
V2	chip_pin_mux	chip_padctrl_attributes	2.469m	4.448ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	2.469m	4.448ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	3.137m	3.671ms	0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.994m	6.204ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	3.368m	3.228ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	1.381m	2.362ms	1	1	100.00
		chip_tap_straps_testunlock0	7.449m	7.351ms	1	1	100.00
		chip_tap_straps_rma	1.057m	2.382ms	1	1	100.00
		chip_tap_straps_prod	9.173m	9.464ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	1.837m	2.814ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	11.851m	8.842ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	5.979m	5.613ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	5.979m	5.613ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	9.975m	7.969ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	28.626m	17.290ms	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	6.435m	4.085ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	10.551m	6.132ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	54.647m	18.155ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.510m	3.351ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	12.789m	7.323ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.248m	3.421ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	27.870m	13.050ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.372m	3.512ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.182m	4.263ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.520m	2.994ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	3.781m	3.078ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	6.219m	7.161ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.382m	5.283ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	2.034m	2.407ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.382m	5.283ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	2.302m	2.690ms	1	1	100.00
		chip_sw_aes_smoketest	2.311m	2.530ms	1	1	100.00
		chip_sw_aon_timer_smoketest	3.367m	3.302ms	1	1	100.00
		chip_sw_clkmgr_smoketest	2.984m	2.831ms	1	1	100.00
		chip_sw_csrng_smoketest	2.479m	2.983ms	1	1	100.00
		chip_sw_entropy_src_smoketest	13.338m	7.474ms	1	1	100.00
		chip_sw_gpio_smoketest	2.527m	3.028ms	1	1	100.00
		chip_sw_hmac_smoketest	3.439m	3.075ms	1	1	100.00
		chip_sw_kmac_smoketest	2.829m	3.163ms	1	1	100.00
		chip_sw_otbn_smoketest	8.463m	5.645ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	4.812m	6.477ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	4.070m	6.463ms	1	1	100.00
		chip_sw_rv_plic_smoketest	2.341m	3.183ms	1	1	100.00
		chip_sw_rv_timer_smoketest	2.670m	2.245ms	1	1	100.00
		chip_sw_rstmgr_smoketest	2.791m	2.978ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	1.768m	2.167ms	1	1	100.00
		chip_sw_uart_smoketest	3.023m	2.854ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	2.276m	2.385ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	5.487m	4.624ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	2.189h	61.605ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	41.119m	15.676ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	2.976m	6.112ms	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	2.825m	3.175ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	2.566m	3.002ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	2.027h	53.706ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	2.036h	55.749ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	3.006m	3.753ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	3.006m	3.753ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	52.750m	29.985ms	1	1	100.00
		chip_same_csr_outstanding	21.975m	14.494ms	1	1	100.00
		chip_csr_hw_reset	3.998m	6.222ms	1	1	100.00
		chip_csr_rw	5.778m	6.351ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	52.750m	29.985ms	1	1	100.00
		chip_same_csr_outstanding	21.975m	14.494ms	1	1	100.00
		chip_csr_hw_reset	3.998m	6.222ms	1	1	100.00
		chip_csr_rw	5.778m	6.351ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	38.760s	1.600ms	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	4.810s	42.953us	1	1	100.00
		xbar_smoke_large_delays	42.240s	6.691ms	1	1	100.00
		xbar_smoke_slow_rsp	38.350s	4.283ms	1	1	100.00
		xbar_random_zero_delays	18.540s	347.365us	1	1	100.00
		xbar_random_large_delays	1.662m	16.385ms	1	1	100.00
		xbar_random_slow_rsp	1.515m	10.598ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	28.160s	1.116ms	1	1	100.00
		xbar_error_and_unmapped_addr	19.080s	765.304us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	15.780s	664.635us	1	1	100.00
		xbar_error_and_unmapped_addr	19.080s	765.304us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	29.550s	601.650us	1	1	100.00
		xbar_access_same_device_slow_rsp	9.731m	64.842ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	18.300s	403.888us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	6.087m	16.705ms	1	1	100.00
		xbar_stress_all_with_error	1.186m	3.605ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	1.061m	177.309us	1	1	100.00
		xbar_stress_all_with_reset_error	2.236m	1.290ms	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	41.119m	15.676ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	37.148m	28.607ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	42.870m	15.020ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	34.141m	11.269ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	44.212m	15.377ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	43.145m	15.924ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	42.924m	15.742ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	42.041m	15.469ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	18.880s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	17.870s	10.260us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	17.270s	10.180us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	16.840s	10.140us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	17.680s	10.180us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	16.530s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	24.310s	10.300us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	16.630s	10.200us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	16.830s	10.260us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	16.640s	10.360us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	15.880s	10.120us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	20.660s	10.160us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	16.470s	10.160us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	21.490s	10.160us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	16.570s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	16.330s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	16.480s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	17.040s	10.320us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	19.560s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	22.390s	10.320us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	16.360s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	15.980s	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	16.430s	10.120us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	20.780s	10.320us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	19.580s	10.400us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	32.960m	12.203ms	1	1	100.00
		rom_e2e_asm_init_dev	41.327m	15.541ms	1	1	100.00
		rom_e2e_asm_init_prod	41.154m	15.807ms	1	1	100.00
		rom_e2e_asm_init_prod_end	41.017m	14.961ms	1	1	100.00
		rom_e2e_asm_init_rma	40.867m	14.543ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	38.690m	14.923ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	40.040m	14.907ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	38.182m	15.329ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	42.173m	16.048ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	50.293m	35.238ms	0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	50.293m	35.238ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	2.669m	2.827ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.510m	3.351ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	1.876m	2.510ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	2.898m	3.113ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	24.741m	11.332ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	2.321m	2.611ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	4.068m	5.221ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	5.722m	4.831ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	9.631m	5.997ms	1	1	100.00
		chip_plic_all_irqs_10	4.552m	3.697ms	1	1	100.00
		chip_plic_all_irqs_20	6.295m	4.072ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	3.981m	4.006ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	17.047m	12.497ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	5.678m	5.778ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	2.136m	2.996ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings			0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	14.004m	7.013ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	16.385m	7.696ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	13.349m	7.589ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	2.079h	256.062ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	4.228m	4.254ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	4.812m	6.477ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	4.228m	4.254ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	6.859m	6.603ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	6.859m	6.603ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	4.239m	7.342ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	4.868m	5.564ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	8.782m	6.485ms	1	1	100.00
		chip_sw_aes_idle	2.898m	3.113ms	1	1	100.00
		chip_sw_hmac_enc_idle	2.135m	3.146ms	1	1	100.00
		chip_sw_kmac_idle	2.392m	2.811ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	3.563m	4.021ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	3.452m	3.964ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	4.537m	5.254ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	4.021m	3.816ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	10.523m	10.518ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	6.498m	4.320ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	6.704m	5.108ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.119m	3.726ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.542m	4.738ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	6.303m	4.358ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	6.192m	5.066ms	1	1	100.00
		chip_sw_ast_clk_outputs	9.975m	7.969ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	10.644m	11.758ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.119m	3.726ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.542m	4.738ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	6.435m	4.085ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	10.551m	6.132ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	54.647m	18.155ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.510m	3.351ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	12.789m	7.323ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.248m	3.421ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	27.870m	13.050ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.372m	3.512ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.182m	4.263ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.520m	2.994ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	2.146m	2.740ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	7.119m	5.050ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	9.524m	6.760ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	50.671m	25.186ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	2.497m	3.473ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.366m	2.829ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	21.292m	12.937ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	2.684m	3.735ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	6.628m	5.510ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	16.708m	17.737ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	54.058m	32.006ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	9.975m	7.969ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	5.422m	4.469ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	3.788m	3.955ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	5.722m	4.831ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	14.004m	7.013ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	12.497m	5.783ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	2.062m	2.456ms	0	1	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	5.885m	6.617ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	2.121m	2.665ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	1.065h	23.952ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	2.579m	2.850ms	1	1	100.00
		chip_sw_edn_entropy_reqs	10.256m	7.090ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	2.579m	2.850ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	12.497m	5.783ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	2.193m	3.005ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	18.082m	17.364ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	9.726m	5.938ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	10.551m	6.132ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	6.298m	4.109ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	6.435m	4.085ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	1.092h	43.836ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	18.082m	17.364ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	4.061m	3.596ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	13.783m	7.789ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.029m	5.002ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	1.092h	43.836ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.029m	5.002ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.029m	5.002ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	4.029m	5.002ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.029m	5.002ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	5.722m	4.831ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	2.136m	4.796ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	9.000m	4.504ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	7.842m	5.280ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	7.842m	5.280ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	3.147m	3.086ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.248m	3.421ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	2.135m	3.146ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	2.930m	3.133ms	0	1	0.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	5.564m	3.998ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	5.538m	4.317ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	6.931m	5.308ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	6.506m	4.777ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	4.486m	3.630ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	13.783m	7.789ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	27.870m	13.050ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	16.419m	7.813ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	24.741m	11.332ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	47.758m	15.583ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	2.046m	2.355ms	1	1	100.00
		chip_sw_kmac_mode_kmac	2.647m	3.239ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.372m	3.512ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	13.783m	7.789ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	3.838m	7.345ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	2.941m	2.744ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	11.883m	5.930ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	2.392m	2.811ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	4.068m	5.221ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	1.381m	2.362ms	1	1	100.00
		chip_tap_straps_rma	1.057m	2.382ms	1	1	100.00
		chip_tap_straps_prod	9.173m	9.464ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	3.079m	3.264ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	3.838m	7.345ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	3.838m	7.345ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	3.838m	7.345ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	14.649m	7.229ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	4.029m	5.002ms	1	1	100.00
		chip_sw_flash_rma_unlocked	1.092h	43.836ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.102m	3.091ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	9.325m	8.158ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	7.611m	6.304ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	6.811m	6.904ms	0	1	0.00
		chip_sw_lc_ctrl_transition	3.838m	7.345ms	1	1	100.00
		chip_sw_keymgr_key_derivation	13.783m	7.789ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	5.045m	8.447ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	10.321m	8.620ms	1	1	100.00
		chip_prim_tl_access	2.136m	4.796ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	10.644m	11.758ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	6.498m	4.320ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	6.704m	5.108ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.119m	3.726ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.542m	4.738ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	6.303m	4.358ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	6.192m	5.066ms	1	1	100.00
		chip_tap_straps_dev	1.381m	2.362ms	1	1	100.00
		chip_tap_straps_rma	1.057m	2.382ms	1	1	100.00
		chip_tap_straps_prod	9.173m	9.464ms	1	1	100.00
		chip_rv_dm_lc_disabled	1.260m	4.864ms	0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	1.912m	3.297ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.317m	3.481ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.218m	2.815ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	3.039m	3.730ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	21.661m	30.098ms	1	1	100.00
		chip_rv_dm_lc_disabled	1.260m	4.864ms	0	1	0.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.143h	47.631ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	1.036h	48.385ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	10.171m	11.133ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	1.069h	45.652ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	21.661m	30.098ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.525m	2.966ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.007m	2.624ms	1	1	100.00
		rom_volatile_raw_unlock	52.760s	1.922ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	57.606m	17.306ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	54.647m	18.155ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	8.782m	6.485ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	8.782m	6.485ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	8.782m	6.485ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	5.127m	3.743ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	3.838m	7.345ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	18.082m	17.364ms	1	1	100.00
		chip_sw_otbn_mem_scramble	5.127m	3.743ms	1	1	100.00
		chip_sw_keymgr_key_derivation	13.783m	7.789ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	6.854m	5.164ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	1.965m	2.586ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	18.082m	17.364ms	1	1	100.00
		chip_sw_otbn_mem_scramble	5.127m	3.743ms	1	1	100.00
		chip_sw_keymgr_key_derivation	13.783m	7.789ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	6.854m	5.164ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	1.965m	2.586ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	3.838m	7.345ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	4.193m	3.744ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	3.079m	3.264ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.102m	3.091ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	9.325m	8.158ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	7.611m	6.304ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	6.811m	6.904ms	0	1	0.00
		chip_sw_lc_ctrl_transition	3.838m	7.345ms	1	1	100.00
		chip_prim_tl_access	2.136m	4.796ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	2.136m	4.796ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	19.026m	9.701ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	3.617m	7.709ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	13.120m	23.529ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	5.041m	7.212ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	4.235m	6.764ms	0	1	0.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	5.575m	6.348ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	15.463m	22.694ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	6.571m	9.582ms	0	1	0.00
		chip_sw_aon_timer_wdog_bite_reset	6.859m	6.603ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	13.537m	9.827ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	5.259m	4.254ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	3.617m	7.709ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	2.795m	3.943ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	4.638m	5.617ms	0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	3.832m	7.102ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	4.937m	6.425ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	8.348m	12.898ms	0	1	0.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	10.915m	8.327ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	15.375m	10.949ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	31.283m	26.421ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	1.980m	3.037ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	5.722m	4.831ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	5.045m	8.447ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	5.045m	8.447ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	15.375m	10.949ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	8.348m	12.898ms	0	1	0.00
		chip_sw_pwrmgr_wdog_reset	5.259m	4.254ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	4.812m	6.477ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	4.814m	4.575ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	3.109m	4.439ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	2.608m	3.744ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	17.047m	12.497ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	1.863m	2.418ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	5.722m	4.831ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	16.385m	7.696ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	8.528m	4.701ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	7.831m	4.381ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	2.281m	3.221ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	1.965m	2.586ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	3.109m	4.439ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	3.109m	4.439ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	18.817m	15.606ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	14.392m	13.410ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	4.814m	4.575ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	4.417m	4.963ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	4.188m	6.211ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	1.057m	2.382ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	1.260m	4.864ms	0	1	0.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	9.631m	5.997ms	1	1	100.00
		chip_plic_all_irqs_10	4.552m	3.697ms	1	1	100.00
		chip_plic_all_irqs_20	6.295m	4.072ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	1.818m	2.394ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	2.592m	2.452ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	41.119m	15.676ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	8.422m	7.243ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	2.418m	2.441ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	2.915m	2.982ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	2.444m	3.152ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	6.854m	5.164ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.182m	4.263ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	6.850m	8.445ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	5.958m	7.876ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	10.321m	8.620ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	5.722m	4.831ms	1	1	100.00
		chip_sw_data_integrity_escalation	5.979m	5.613ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	10.915m	8.327ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	17.958m	23.045ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	2.086m	2.420ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	3.776m	4.006ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	4.894m	3.819ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	17.958m	23.045ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	17.958m	23.045ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	14.147m	11.774ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	14.147m	11.774ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	3.786m	4.939ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	50.293m	35.238ms	0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	2.854m	2.974ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	2.550m	2.735ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	4.763m	3.796ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	5.153m	3.990ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	17.033m	7.877ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.410h	31.618ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	30.330m	12.111ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	2.613m	2.733ms	1	1	100.00
V2		TOTAL			230	275	83.64
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	3.182m	3.117ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	1.627m	2.771ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_sw_coremark	chip_sw_coremark	2.665h	71.892ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	17.409m	6.033ms	1	1	100.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	19.012m	10.757ms	1	1	100.00
		rom_e2e_jtag_debug_dev	2.753m	2.926ms	0	1	0.00
		rom_e2e_jtag_debug_rma	17.913m	11.629ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	2.958m	4.130ms	1	1	100.00
		rom_e2e_jtag_inject_dev	2.801m	4.294ms	1	1	100.00
		rom_e2e_jtag_inject_rma	3.986m	5.020ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	8.945s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	9.000m	5.225ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	4.778m	3.067ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	14.600m	5.701ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	23.227m	10.249ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.390m	1.955ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	9.095m	5.133ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	1.004m	2.065ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	3.422m	3.520ms	0	1	0.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	4.118m	6.191ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	4.964m	4.978ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	15.375m	10.949ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	19.012m	10.757ms	1	1	100.00
		rom_e2e_jtag_debug_dev	2.753m	2.926ms	0	1	0.00
		rom_e2e_jtag_debug_rma	17.913m	11.629ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	7.087m	5.800ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	5.722m	4.831ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.591h	38.091ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.591h	38.091ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	3.113m	3.553ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	5.515m	4.791ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	50.910m	18.588ms	1	1	100.00
V3		TOTAL			20	23	86.96
	Unmapped tests	chip_sival_flash_info_access	3.179m	3.418ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	5.751m	4.427ms	1	1	100.00
		chip_sw_otp_ctrl_rot_auth_config	35.642m	22.745ms	0	1	0.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	3.076m	2.836ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	2.691m	3.386ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	3.465m	3.425ms	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	12.782s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	3.851m	3.591ms	1	1	100.00
		TOTAL			275	326	84.36

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.28605136424092159522337048488254452760234221746145178836212921810246944846208
    Line 496, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.83145590661398767903789068526196953742934495740562343759979404080258014672867
    Line 515, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.5353281453762441849688623693043933091105483047290323889041242991362783716094
    Line 534, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.108539330292357155659856123810545195141686237875531642718999990600034862459556
    Line 530, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.35729978356834546360336427336696813556248509982668355662699267233188039988873
    Line 540, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.88739412485222056543979397252946994624169286183458273836622680285557542218420
    Line 472, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.89097134581635427930343033455571390156727417949759944081568087275357825092371
    Line 472, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.55720182552108359936478558707794819525853440388697704229827162961076122421817
    Line 472, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.90777991326387204549176435923696404019243551373337074772306768780667279368932
    Line 472, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.76198820384803317255281241087065488983428700795563696366875059605978097415563
    Line 518, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(rstreqs[*] && (reset_cause == HwReq))' has 4 failures:
- Test chip_sw_pwrmgr_random_sleep_all_reset_reqs has 1 failures.
  - 0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.14236293294647233447167584538817136569190138062160684423355557669920797489694
    Line 425, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest/run.log
```
      Offending '(rstreqs[1] && (reset_cause == HwReq))'
  UVM_ERROR @ 12897.641000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
  UVM_INFO @ 12897.641000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_pwrmgr_deep_sleep_all_reset_reqs has 1 failures.
  - 0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.78706942577786564740794928516770863333944908545352565300181194541874071982531
    Line 409, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest/run.log
```
      Offending '(rstreqs[1] && (reset_cause == HwReq))'
  UVM_ERROR @ 9581.814000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
  UVM_INFO @ 9581.814000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_pwrmgr_deep_sleep_por_reset has 1 failures.
  - 0.chip_sw_pwrmgr_deep_sleep_por_reset.63121345759487083410336384130383390571223092222537589490523299025682657443160
    Line 407, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_por_reset/latest/run.log
```
      Offending '(rstreqs[0] && (reset_cause == HwReq))'
  UVM_ERROR @ 6763.948000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
  UVM_INFO @ 6763.948000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_pwrmgr_random_sleep_power_glitch_reset has 1 failures.
  - 0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.33490037574306902681533522242488379321940085828611535801029663450003640392207
    Line 399, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest/run.log
```
      Offending '(rstreqs[1] && (reset_cause == HwReq))'
  UVM_ERROR @ 5617.017000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
  UVM_INFO @ 5617.017000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.408996611034501423480624214681877610542755448581898271360179398305365619592
    Line 500, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.32938315092238260205251897518430709282061661121965711747862989086024130426392
    Line 553, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.20542032657369436972661523775472884793261032981716573668590329098203670765271
    Line 525, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' has 2 failures:
- Test chip_sw_otp_ctrl_escalation has 1 failures.
  - 0.chip_sw_otp_ctrl_escalation.13176346227017663318782679704975330860609791160563899217753038144565647067564
    Line 398, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_escalation/latest/run.log
```
      Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
  UVM_ERROR @ 3519.952558 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
  UVM_INFO @ 3519.952558 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_csrng_fuse_en_sw_app_read_test has 1 failures.
  - 0.chip_sw_csrng_fuse_en_sw_app_read_test.34454854038124727147363896807583742476734284680936910454188276607079772793624
    Line 390, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
      Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
  UVM_ERROR @ 2456.283312 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
  UVM_INFO @ 2456.283312 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 2 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.90215743862298247282430940339767879226784522810541679281390763181969382737397
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 1.988s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.34411508358685780360998305646447795383477183714246930217713988212366603363594
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 0.150s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.79942876953538701860491189968234307064853835056841478355681397152104167652874
    Line 564, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.74601369483590525103702073477398101806652141468017240147450471961758480773820
    Line 501, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.98949619352893374147963810852129181168566743312565816598802480596846173545700
    Line 630, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.31125231453426104426578766574886932271866594617395666471153883243263711540626
    Line 513, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [*] vs *xz [z]) for MIO[*] has 1 failures:
- Test chip_sw_sleep_pin_mio_dio_val has 1 failures.
  - 0.chip_sw_sleep_pin_mio_dio_val.94422009253466014067238409515957290368006325886032285712771081681914517800581
    Line 561, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_pin_mio_dio_val/latest/run.log
```
  UVM_ERROR @ 3671.090000 us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (0x0 [0] vs 0xz [z]) for MIO[30]
  UVM_INFO @ 3671.090000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.60656757647288203625135601921736450806200548374427603589140370616806474409447
    Line 402, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 2440.574200 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 2440.574200 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to * has 1 failures:
- Test chip_sw_otp_ctrl_lc_signals_rma has 1 failures.
  - 0.chip_sw_otp_ctrl_lc_signals_rma.21422216928670760424416259698854337561734440260546125921072641683347338589358
    Line 433, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_rma/latest/run.log
```
  UVM_ERROR @ 6903.594570 us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to 0x0
  UVM_INFO @ 6903.594570 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_rot_auth_config_test_sim_dv(sw/device/tests/otp_ctrl_rot_auth_config_test.c:22)] CHECK-STATUS-fail: @@@:* = ErrorError has 1 failures:
- Test chip_sw_otp_ctrl_rot_auth_config has 1 failures.
  - 0.chip_sw_otp_ctrl_rot_auth_config.91334909385966102034354968327167021657542613857149932893988313142387241727296
    Line 436, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_rot_auth_config/latest/run.log
```
  UVM_ERROR @ 22744.629528 us: (sw_logger_if.sv:526) [otp_ctrl_rot_auth_config_test_sim_dv(sw/device/tests/otp_ctrl_rot_auth_config_test.c:22)] CHECK-STATUS-fail: @@@:0 = ErrorError
  UVM_INFO @ 22744.629528 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@78590) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.93950598053755170764554414656692476660631975294741901093625822433167692458398
Line 418, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 4439.199592 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@78590) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h1  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4439.199592 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:200)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor has 1 failures:
- Test chip_sw_sysrst_ctrl_ec_rst_l has 1 failures.
  - 0.chip_sw_sysrst_ctrl_ec_rst_l.110297937358827214227643564435488461938852912819161045410018839694601261986287
    Line 402, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_ec_rst_l/latest/run.log
```
  UVM_ERROR @ 11774.455831 us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:200)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor
  UVM_INFO @ 11774.455831 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 1 failures.
  - 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.77605159468533953803700377654912464049860653524528161058469638205557642855651
    Line 414, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  UVM_ERROR @ 35238.247937 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 35238.247937 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.78909279784460365077998143300912727885530717953692366292720492296750982558172
    Line 394, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 2611.468400 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 42!
  UVM_INFO @ 2611.468400 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.32017140310136136454564945729733998637161333721322425243906977307133444860221
    Line 391, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 2995.579451 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 2995.579451 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job timed out after * minutes has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_pings has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_pings.45750056042799024614021309003776386444410169990482188908046092937735951125074
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest/run.log
```
  Job timed out after 240 minutes
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: *. has 1 failures:
- Test chip_sw_hmac_oneshot has 1 failures.
  - 0.chip_sw_hmac_oneshot.34335681864701280485751713516832588873632116726514372140611670598677258327701
    Line 401, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_oneshot/latest/run.log
```
  UVM_ERROR @ 3133.182850 us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: 8000534a.
  UVM_INFO @ 3133.182850 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@267500) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.98771678533100411006370760856471472690440553704966344731001363504445789230267
Line 215, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 3752.586888 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@267500) { a_addr: 'h1061c  a_data: 'h6ceb322b  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'ha  a_opcode: 'h4  a_user: 'h1a21d  d_param: 'h0  d_source: 'ha  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3752.586888 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_vseq.sv:642) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 1 failures:
- Test chip_rv_dm_lc_disabled has 1 failures.
  - 0.chip_rv_dm_lc_disabled.25350298968200963752032352016696444331528051658319313768657692581651988097737
    Line 208, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log
```
  UVM_ERROR @ 4863.766108 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x105e4 read out mismatch
  UVM_INFO @ 4863.766108 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.24334122928941691034961438018526448890805849265378988693558302658614938382180
    Line 395, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 3175.300000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3175.300000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.21358637043335447193714921840186950902144932135461724854088596936435357283601
    Line 402, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 3002.300000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3002.300000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.104713664550465636131598683720949943607179153385511602008671031623374807042940
    Line 415, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 17289.666452 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 17289.666452 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.6521952433296332409267659352526274414524870931898958540394426364202320613627
    Line 530, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.94884461650090042681552440861875553982506333863949782223639291929644982111333
    Line 521, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (jtag_rv_debugger.sv:784) [debugger] Index * appears to be out of bounds has 1 failures:
- Test rom_e2e_jtag_debug_dev has 1 failures.
  - 0.rom_e2e_jtag_debug_dev.80970552941219548718297434590643112823648020526847064112176995512134665580480
    Line 447, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log
```
  UVM_ERROR @ 2925.708929 us: (jtag_rv_debugger.sv:784) [debugger] Index 3 appears to be out of bounds
  UVM_INFO @ 2925.708929 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33018) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

0.chip_csr_mem_rw_with_rand_reset.12367518332704276115074114734256936955859311731872615935313470913139963824875
Line 221, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2172.279624 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33018) { a_addr: 'h10478  a_data: 'hc683c852  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h22  a_opcode: 'h4  a_user: 'h195fd  d_param: 'h0  d_source: 'h22  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2172.279624 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---