ADC_CTRL Simulation Results

Wednesday November 05 2025 19:20:47 UTC

GitHub Revision: 9baed2b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	10.510s	5.735ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	1.930s	668.929us	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	0.950s	571.785us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	17.090s	53.863ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	1.630s	900.624us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	1.310s	495.047us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	0.950s	571.785us	1	1	100.00
		adc_ctrl_csr_aliasing	1.630s	900.624us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	3.567m	484.001ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	8.903m	323.676ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	6.999m	497.650ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	12.361m	496.405ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	2.501m	172.473ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	10.764m	392.694ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	1.588m	353.870ms	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	16.150m	2.000s	0	1	0.00
V2	poweron_counter	adc_ctrl_poweron_counter	4.860s	4.133ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	20.990s	41.398ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	53.230s	110.755ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	39.110s	176.830ms	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	1.000s	348.274us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	1.160s	437.325us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	2.180s	519.625us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	2.180s	519.625us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	1.930s	668.929us	1	1	100.00
		adc_ctrl_csr_rw	0.950s	571.785us	1	1	100.00
		adc_ctrl_csr_aliasing	1.630s	900.624us	1	1	100.00
		adc_ctrl_same_csr_outstanding	4.090s	2.507ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	1.930s	668.929us	1	1	100.00
		adc_ctrl_csr_rw	0.950s	571.785us	1	1	100.00
		adc_ctrl_csr_aliasing	1.630s	900.624us	1	1	100.00
		adc_ctrl_same_csr_outstanding	4.090s	2.507ms	1	1	100.00
V2		TOTAL			15	16	93.75
V2S	tl_intg_err	adc_ctrl_sec_cm	14.210s	7.438ms	1	1	100.00
		adc_ctrl_tl_intg_err	6.050s	8.719ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	6.050s	8.719ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	5.720s	2.809ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			24	25	96.00

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test adc_ctrl_clock_gating has 1 failures.

    • 0.adc_ctrl_clock_gating.38302796623412868381736409822935260543831319393171922491362365983201408050315
      Line 182, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/0.adc_ctrl_clock_gating/latest/run.log

        UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---