EDN Simulation Results

Wednesday November 05 2025 19:20:47 UTC

GitHub Revision: 9baed2b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	0.880s	26.598us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.900s	17.444us	1	1	100.00
V1	csr_rw	edn_csr_rw	0.970s	15.334us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	2.500s	265.222us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	1.030s	61.194us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.090s	73.716us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.970s	15.334us	1	1	100.00
		edn_csr_aliasing	1.030s	61.194us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	1.130s	54.446us	1	1	100.00
V2	csrng_commands	edn_genbits	1.130s	54.446us	1	1	100.00
V2	genbits	edn_genbits	1.130s	54.446us	1	1	100.00
V2	interrupts	edn_intr	0.790s	32.493us	1	1	100.00
V2	alerts	edn_alert	1.040s	29.224us	1	1	100.00
V2	errs	edn_err	0.980s	18.294us	1	1	100.00
V2	disable	edn_disable	0.760s	21.528us	1	1	100.00
		edn_disable_auto_req_mode	0.980s	33.747us	1	1	100.00
V2	stress_all	edn_stress_all	2.230s	255.368us	1	1	100.00
V2	intr_test	edn_intr_test	0.750s	25.949us	1	1	100.00
V2	alert_test	edn_alert_test	0.760s	36.014us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	1.380s	91.362us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	1.380s	91.362us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.900s	17.444us	1	1	100.00
		edn_csr_rw	0.970s	15.334us	1	1	100.00
		edn_csr_aliasing	1.030s	61.194us	1	1	100.00
		edn_same_csr_outstanding	0.940s	61.161us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.900s	17.444us	1	1	100.00
		edn_csr_rw	0.970s	15.334us	1	1	100.00
		edn_csr_aliasing	1.030s	61.194us	1	1	100.00
		edn_same_csr_outstanding	0.940s	61.161us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	6.020s	2.778ms	1	1	100.00
		edn_tl_intg_err	1.920s	188.063us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	0.890s	22.525us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	1.040s	29.224us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	6.020s	2.778ms	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	6.020s	2.778ms	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	6.020s	2.778ms	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	6.020s	2.778ms	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.040s	29.224us	1	1	100.00
		edn_sec_cm	6.020s	2.778ms	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.040s	29.224us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	1.920s	188.063us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	38.990s	9.374ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00