ENTROPY_SRC/RNG_4BITS Simulation Results

Wednesday November 05 2025 19:20:47 UTC

GitHub Revision: 9baed2b

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 2.000s 108.487us 1 1 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 2.000s 74.343us 1 1 100.00
V1 csr_rw entropy_src_csr_rw 2.000s 44.125us 1 1 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 6.000s 1.392ms 1 1 100.00
V1 csr_aliasing entropy_src_csr_aliasing 5.000s 818.848us 1 1 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 1.000s 58.187us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 2.000s 44.125us 1 1 100.00
entropy_src_csr_aliasing 5.000s 818.848us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 firmware entropy_src_smoke 2.000s 108.487us 1 1 100.00
entropy_src_rng 4.917m 17.032ms 1 1 100.00
entropy_src_fw_ov 6.250m 20.043ms 1 1 100.00
V2 firmware_mode entropy_src_fw_ov 6.250m 20.043ms 1 1 100.00
V2 rng_mode entropy_src_rng 4.917m 17.032ms 1 1 100.00
V2 rng_max_rate entropy_src_rng_max_rate 59.000s 14.228ms 1 1 100.00
V2 health_checks entropy_src_rng 4.917m 17.032ms 1 1 100.00
V2 conditioning entropy_src_rng 4.917m 17.032ms 1 1 100.00
V2 interrupts entropy_src_rng 4.917m 17.032ms 1 1 100.00
entropy_src_intr 3.000s 79.500us 1 1 100.00
V2 alerts entropy_src_rng 4.917m 17.032ms 1 1 100.00
entropy_src_functional_alerts 5.000s 344.337us 1 1 100.00
V2 stress_all entropy_src_stress_all 55.000s 16.650ms 1 1 100.00
V2 functional_errors entropy_src_functional_errors 2.000s 107.123us 1 1 100.00
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 4.000s 77.064us 1 1 100.00
V2 intr_test entropy_src_intr_test 2.000s 23.184us 1 1 100.00
V2 alert_test entropy_src_alert_test 3.000s 30.092us 1 1 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 5.000s 638.553us 1 1 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 5.000s 638.553us 1 1 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 2.000s 74.343us 1 1 100.00
entropy_src_csr_rw 2.000s 44.125us 1 1 100.00
entropy_src_csr_aliasing 5.000s 818.848us 1 1 100.00
entropy_src_same_csr_outstanding 2.000s 77.239us 1 1 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 2.000s 74.343us 1 1 100.00
entropy_src_csr_rw 2.000s 44.125us 1 1 100.00
entropy_src_csr_aliasing 5.000s 818.848us 1 1 100.00
entropy_src_same_csr_outstanding 2.000s 77.239us 1 1 100.00
V2 TOTAL 12 12 100.00
V2S tl_intg_err entropy_src_sec_cm 3.000s 96.649us 1 1 100.00
entropy_src_tl_intg_err 3.000s 97.072us 1 1 100.00
V2S sec_cm_config_regwen entropy_src_rng 4.917m 17.032ms 1 1 100.00
entropy_src_cfg_regwen 3.000s 21.986us 1 1 100.00
V2S sec_cm_config_mubi entropy_src_rng 4.917m 17.032ms 1 1 100.00
V2S sec_cm_config_redun entropy_src_rng 4.917m 17.032ms 1 1 100.00
V2S sec_cm_intersig_mubi entropy_src_rng 4.917m 17.032ms 1 1 100.00
entropy_src_fw_ov 6.250m 20.043ms 1 1 100.00
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 2.000s 107.123us 1 1 100.00
entropy_src_sec_cm 3.000s 96.649us 1 1 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 2.000s 107.123us 1 1 100.00
entropy_src_sec_cm 3.000s 96.649us 1 1 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 4.917m 17.032ms 1 1 100.00
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 2.000s 107.123us 1 1 100.00
entropy_src_sec_cm 3.000s 96.649us 1 1 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 2.000s 107.123us 1 1 100.00
entropy_src_sec_cm 3.000s 96.649us 1 1 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 2.000s 107.123us 1 1 100.00
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 5.000s 344.337us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 3.000s 97.072us 1 1 100.00
V2S TOTAL 3 3 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 25.000s 16.582ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 22 22 100.00