HMAC Simulation Results

Wednesday November 05 2025 19:20:47 UTC

GitHub Revision: 9baed2b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 4.920s 421.550us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 0.830s 16.151us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.040s 53.904us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 8.460s 501.522us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 5.180s 1.703ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 1.130s 36.762us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.040s 53.904us 1 1 100.00
hmac_csr_aliasing 5.180s 1.703ms 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 7.000s 564.537us 1 1 100.00
V2 back_pressure hmac_back_pressure 1.104m 19.650ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 8.480s 510.246us 1 1 100.00
hmac_test_sha384_vectors 8.424m 135.702ms 1 1 100.00
hmac_test_sha512_vectors 6.610m 52.495ms 1 1 100.00
hmac_test_hmac256_vectors 8.390s 296.673us 1 1 100.00
hmac_test_hmac384_vectors 16.900s 372.806us 1 1 100.00
hmac_test_hmac512_vectors 10.700s 359.070us 1 1 100.00
V2 burst_wr hmac_burst_wr 8.850s 767.209us 1 1 100.00
V2 datapath_stress hmac_datapath_stress 0.830s 17.652us 1 1 100.00
V2 error hmac_error 1.383m 6.014ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 39.300s 2.962ms 1 1 100.00
V2 save_and_restore hmac_smoke 4.920s 421.550us 1 1 100.00
hmac_long_msg 7.000s 564.537us 1 1 100.00
hmac_back_pressure 1.104m 19.650ms 1 1 100.00
hmac_datapath_stress 0.830s 17.652us 1 1 100.00
hmac_burst_wr 8.850s 767.209us 1 1 100.00
hmac_stress_all 17.548m 163.063ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 4.920s 421.550us 1 1 100.00
hmac_long_msg 7.000s 564.537us 1 1 100.00
hmac_back_pressure 1.104m 19.650ms 1 1 100.00
hmac_datapath_stress 0.830s 17.652us 1 1 100.00
hmac_wipe_secret 39.300s 2.962ms 1 1 100.00
hmac_test_sha256_vectors 8.480s 510.246us 1 1 100.00
hmac_test_sha384_vectors 8.424m 135.702ms 1 1 100.00
hmac_test_sha512_vectors 6.610m 52.495ms 1 1 100.00
hmac_test_hmac256_vectors 8.390s 296.673us 1 1 100.00
hmac_test_hmac384_vectors 16.900s 372.806us 1 1 100.00
hmac_test_hmac512_vectors 10.700s 359.070us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 4.920s 421.550us 1 1 100.00
hmac_long_msg 7.000s 564.537us 1 1 100.00
hmac_back_pressure 1.104m 19.650ms 1 1 100.00
hmac_datapath_stress 0.830s 17.652us 1 1 100.00
hmac_burst_wr 8.850s 767.209us 1 1 100.00
hmac_error 1.383m 6.014ms 1 1 100.00
hmac_wipe_secret 39.300s 2.962ms 1 1 100.00
hmac_test_sha256_vectors 8.480s 510.246us 1 1 100.00
hmac_test_sha384_vectors 8.424m 135.702ms 1 1 100.00
hmac_test_sha512_vectors 6.610m 52.495ms 1 1 100.00
hmac_test_hmac256_vectors 8.390s 296.673us 1 1 100.00
hmac_test_hmac384_vectors 16.900s 372.806us 1 1 100.00
hmac_test_hmac512_vectors 10.700s 359.070us 1 1 100.00
hmac_stress_all 17.548m 163.063ms 1 1 100.00
V2 stress_all hmac_stress_all 17.548m 163.063ms 1 1 100.00
V2 alert_test hmac_alert_test 0.780s 11.016us 1 1 100.00
V2 intr_test hmac_intr_test 0.600s 37.445us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.020s 554.592us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.020s 554.592us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 0.830s 16.151us 1 1 100.00
hmac_csr_rw 1.040s 53.904us 1 1 100.00
hmac_csr_aliasing 5.180s 1.703ms 1 1 100.00
hmac_same_csr_outstanding 1.290s 176.336us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 0.830s 16.151us 1 1 100.00
hmac_csr_rw 1.040s 53.904us 1 1 100.00
hmac_csr_aliasing 5.180s 1.703ms 1 1 100.00
hmac_same_csr_outstanding 1.290s 176.336us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.040s 66.580us 1 1 100.00
hmac_tl_intg_err 2.510s 424.961us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 2.510s 424.961us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 4.920s 421.550us 1 1 100.00
V3 stress_reset hmac_stress_reset 3.790s 161.421us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 27.230s 1.924ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 1.040s 223.877us 1 1 100.00
TOTAL 28 28 100.00