I2C Simulation Results

Wednesday November 05 2025 19:20:47 UTC

GitHub Revision: 9baed2b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	20.360s	7.979ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	16.880s	792.840us	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.630s	32.801us	1	1	100.00
V1	csr_rw	i2c_csr_rw	0.650s	19.239us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	1.860s	571.499us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.000s	28.848us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	0.810s	33.277us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.650s	19.239us	1	1	100.00
		i2c_csr_aliasing	1.000s	28.848us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	0.760s	16.131us	0	1	0.00
V2	host_stress_all	i2c_host_stress_all	0.680s	4.660us	0	1	0.00
V2	host_maxperf	i2c_host_perf	4.571m	600.000ms	0	1	0.00
V2	host_override	i2c_host_override	0.690s	17.814us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	3.757m	4.993ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	1.436m	2.479ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.020s	173.541us	1	1	100.00
		i2c_host_fifo_fmt_empty	13.010s	906.494us	1	1	100.00
		i2c_host_fifo_reset_rx	3.730s	2.640ms	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	44.690s	10.963ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	7.310s	4.344ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.450s	43.082us	0	1	0.00
V2	target_glitch	i2c_target_glitch	1.950s	499.091us	0	1	0.00
V2	target_stress_all	i2c_target_stress_all	3.175m	18.508ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	3.810s	3.573ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	6.090s	976.158us	1	1	100.00
		i2c_target_intr_smoke	2.800s	1.232ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.180s	208.191us	1	1	100.00
		i2c_target_fifo_reset_tx	0.830s	395.845us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	2.411m	61.038ms	1	1	100.00
		i2c_target_stress_rd	6.090s	976.158us	1	1	100.00
		i2c_target_intr_stress_wr	56.350s	8.672ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	3.810s	4.325ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	8.770s	6.373ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	1.920s	4.046ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	1.990s	556.017us	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	1.960s	456.537us	1	1	100.00
		i2c_target_fifo_watermarks_tx	0.920s	439.968us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	4.571m	600.000ms	0	1	0.00
		i2c_host_perf_precise	1.990s	289.656us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	7.310s	4.344ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	5.140s	494.663us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	1.940s	2.257ms	1	1	100.00
		i2c_target_nack_acqfull_addr	1.690s	1.551ms	1	1	100.00
		i2c_target_nack_txstretch	1.060s	1.085ms	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	4.690s	1.875ms	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	1.610s	1.756ms	1	1	100.00
V2	alert_test	i2c_alert_test	0.700s	17.456us	1	1	100.00
V2	intr_test	i2c_intr_test	0.650s	26.496us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	1.420s	69.630us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	1.420s	69.630us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.630s	32.801us	1	1	100.00
		i2c_csr_rw	0.650s	19.239us	1	1	100.00
		i2c_csr_aliasing	1.000s	28.848us	1	1	100.00
		i2c_same_csr_outstanding	0.920s	26.018us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.630s	32.801us	1	1	100.00
		i2c_csr_rw	0.650s	19.239us	1	1	100.00
		i2c_csr_aliasing	1.000s	28.848us	1	1	100.00
		i2c_same_csr_outstanding	0.920s	26.018us	1	1	100.00
V2		TOTAL			33	38	86.84
V2S	tl_intg_err	i2c_tl_intg_err	1.170s	245.521us	1	1	100.00
		i2c_sec_cm	0.940s	141.438us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	1.170s	245.521us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	15.730s	2.855ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.030s	128.904us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	7.590s	2.864ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			42	50	84.00

Failure Buckets

• UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 3 failures:

  • Test i2c_host_error_intr has 1 failures.

    • 0.i2c_host_error_intr.95253705344829450153819220185071958667066969536683098388632741242226838829532
      Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

        UVM_ERROR @  16130937 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @  16130937 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_host_stress_all has 1 failures.

    • 0.i2c_host_stress_all.39582487015653808201674751773860375688712218002438284867095631918459782824922
      Line 87, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

        UVM_ERROR @   4660491 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @   4660491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.35147111191979440381795467046109408154586345518646892411178515903099655639896
      Line 91, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2864131502 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @ 2864131502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test i2c_host_perf has 1 failures.

    • 0.i2c_host_perf.45991919482300373128500468449218414652417216509522831240544220807260014803561
      Line 77, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_perf/latest/run.log

        UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_target_glitch has 1 failures.

    • 0.i2c_target_glitch.5408885295866928260423756826671824303761560535546403172020474635980874153637
      Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

        UVM_ERROR @ 499090867 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
        UVM_INFO @ 499090867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.36830837791440712574351949365492726825377106987961958703008832628633464141861
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @ 128903777 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 222 [0xde])
        UVM_INFO @ 128903777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.20195621325872995968301929158839317028538868296563889666587245622322305697486
      Line 116, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2855212927 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2855212927 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 1 failures:

  • Test i2c_host_mode_toggle has 1 failures.

    • 0.i2c_host_mode_toggle.53142112854651463791214822429569106863862910837144135711339648200459215085883
      Line 84, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

        UVM_ERROR @  43082001 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
        --> EXP:
        ---------------------------------------------------
        Name            Type                Size  Value
        ---------------------------------------------------