KEYMGR Simulation Results

Wednesday November 05 2025 19:20:47 UTC

GitHub Revision: 9baed2b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	2.150s	60.530us	1	1	100.00
V1	random	keymgr_random	3.300s	591.092us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	0.880s	21.110us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	0.800s	58.132us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	21.380s	1.300ms	1	1	100.00
V1	csr_aliasing	keymgr_csr_aliasing	5.310s	381.822us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	1.300s	153.040us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	0.800s	58.132us	1	1	100.00
		keymgr_csr_aliasing	5.310s	381.822us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	2.180s	46.715us	1	1	100.00
V2	sideload	keymgr_sideload	2.620s	78.705us	1	1	100.00
		keymgr_sideload_kmac	3.070s	95.807us	1	1	100.00
		keymgr_sideload_aes	2.940s	97.925us	1	1	100.00
		keymgr_sideload_otbn	2.770s	105.231us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	1.610s	39.532us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	2.430s	52.934us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	3.160s	112.702us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	4.320s	194.920us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	1.790s	41.756us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	1.460s	147.670us	1	1	100.00
V2	stress_all	keymgr_stress_all	39.290s	1.949ms	1	1	100.00
V2	intr_test	keymgr_intr_test	0.700s	92.649us	1	1	100.00
V2	alert_test	keymgr_alert_test	0.690s	19.081us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	1.440s	342.626us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	1.440s	342.626us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	0.880s	21.110us	1	1	100.00
		keymgr_csr_rw	0.800s	58.132us	1	1	100.00
		keymgr_csr_aliasing	5.310s	381.822us	1	1	100.00
		keymgr_same_csr_outstanding	1.920s	39.946us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	0.880s	21.110us	1	1	100.00
		keymgr_csr_rw	0.800s	58.132us	1	1	100.00
		keymgr_csr_aliasing	5.310s	381.822us	1	1	100.00
		keymgr_same_csr_outstanding	1.920s	39.946us	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	sec_cm_additional_check	keymgr_sec_cm	9.060s	2.239ms	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	9.060s	2.239ms	1	1	100.00
		keymgr_tl_intg_err	2.180s	101.195us	1	1	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	2.010s	286.641us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	2.010s	286.641us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	2.010s	286.641us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	2.010s	286.641us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	4.180s	506.238us	1	1	100.00
V2S	prim_count_check	keymgr_sec_cm	9.060s	2.239ms	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	9.060s	2.239ms	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	2.180s	101.195us	1	1	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	2.010s	286.641us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	2.180s	46.715us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	3.300s	591.092us	1	1	100.00
		keymgr_csr_rw	0.800s	58.132us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	3.300s	591.092us	1	1	100.00
		keymgr_csr_rw	0.800s	58.132us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	3.300s	591.092us	1	1	100.00
		keymgr_csr_rw	0.800s	58.132us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	2.430s	52.934us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	1.790s	41.756us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	1.790s	41.756us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	3.300s	591.092us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	1.490s	34.179us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	9.060s	2.239ms	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	9.060s	2.239ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	9.060s	2.239ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	2.190s	165.908us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	2.430s	52.934us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	9.060s	2.239ms	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	9.060s	2.239ms	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	9.060s	2.239ms	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	2.190s	165.908us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	2.190s	165.908us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	9.060s	2.239ms	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	2.190s	165.908us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	9.060s	2.239ms	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	2.190s	165.908us	1	1	100.00
V2S		TOTAL			6	6	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	4.180s	121.015us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	30	100.00