| V1 |
smoke |
kmac_smoke |
51.930s |
33.770ms |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
kmac_csr_hw_reset |
1.320s |
116.315us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
kmac_csr_rw |
1.170s |
23.141us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
kmac_csr_bit_bash |
11.150s |
298.615us |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
kmac_csr_aliasing |
6.910s |
460.013us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
kmac_csr_mem_rw_with_rand_reset |
2.140s |
37.956us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
kmac_csr_rw |
1.170s |
23.141us |
1 |
1 |
100.00 |
|
|
kmac_csr_aliasing |
6.910s |
460.013us |
1 |
1 |
100.00 |
| V1 |
mem_walk |
kmac_mem_walk |
0.700s |
22.930us |
1 |
1 |
100.00 |
| V1 |
mem_partial_access |
kmac_mem_partial_access |
1.390s |
75.430us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
8 |
8 |
100.00 |
| V2 |
long_msg_and_output |
kmac_long_msg_and_output |
2.212m |
2.346ms |
1 |
1 |
100.00 |
| V2 |
burst_write |
kmac_burst_write |
3.754m |
24.211ms |
1 |
1 |
100.00 |
| V2 |
test_vectors |
kmac_test_vectors_sha3_224 |
26.217m |
41.100ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_sha3_256 |
29.718m |
242.012ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_sha3_384 |
26.551m |
136.429ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_sha3_512 |
12.750s |
939.158us |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_shake_128 |
2.377m |
10.814ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_shake_256 |
1.422m |
2.673ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_kmac |
2.170s |
372.485us |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_kmac_xof |
2.300s |
46.581us |
1 |
1 |
100.00 |
| V2 |
sideload |
kmac_sideload |
9.590s |
557.447us |
1 |
1 |
100.00 |
| V2 |
app |
kmac_app |
3.659m |
27.606ms |
1 |
1 |
100.00 |
| V2 |
app_with_partial_data |
kmac_app_with_partial_data |
2.353m |
7.150ms |
1 |
1 |
100.00 |
| V2 |
entropy_refresh |
kmac_entropy_refresh |
14.300s |
3.725ms |
1 |
1 |
100.00 |
| V2 |
error |
kmac_error |
5.722m |
14.783ms |
1 |
1 |
100.00 |
| V2 |
key_error |
kmac_key_error |
15.840s |
7.044ms |
1 |
1 |
100.00 |
| V2 |
sideload_invalid |
kmac_sideload_invalid |
6.100s |
291.282us |
1 |
1 |
100.00 |
| V2 |
edn_timeout_error |
kmac_edn_timeout_error |
1.190s |
96.074us |
1 |
1 |
100.00 |
| V2 |
entropy_mode_error |
kmac_entropy_mode_error |
1.310s |
53.776us |
1 |
1 |
100.00 |
| V2 |
entropy_ready_error |
kmac_entropy_ready_error |
8.740s |
950.234us |
1 |
1 |
100.00 |
| V2 |
lc_escalation |
kmac_lc_escalation |
1.750s |
50.206us |
1 |
1 |
100.00 |
| V2 |
stress_all |
kmac_stress_all |
24.450s |
1.030ms |
1 |
1 |
100.00 |
| V2 |
intr_test |
kmac_intr_test |
0.760s |
14.318us |
1 |
1 |
100.00 |
| V2 |
alert_test |
kmac_alert_test |
0.840s |
60.655us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
kmac_tl_errors |
1.720s |
87.819us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
kmac_tl_errors |
1.720s |
87.819us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
kmac_csr_hw_reset |
1.320s |
116.315us |
1 |
1 |
100.00 |
|
|
kmac_csr_rw |
1.170s |
23.141us |
1 |
1 |
100.00 |
|
|
kmac_csr_aliasing |
6.910s |
460.013us |
1 |
1 |
100.00 |
|
|
kmac_same_csr_outstanding |
1.220s |
25.865us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
kmac_csr_hw_reset |
1.320s |
116.315us |
1 |
1 |
100.00 |
|
|
kmac_csr_rw |
1.170s |
23.141us |
1 |
1 |
100.00 |
|
|
kmac_csr_aliasing |
6.910s |
460.013us |
1 |
1 |
100.00 |
|
|
kmac_same_csr_outstanding |
1.220s |
25.865us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
26 |
26 |
100.00 |
| V2S |
shadow_reg_update_error |
kmac_shadow_reg_errors |
1.270s |
56.868us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_read_clear_staged_value |
kmac_shadow_reg_errors |
1.270s |
56.868us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_storage_error |
kmac_shadow_reg_errors |
1.270s |
56.868us |
1 |
1 |
100.00 |
| V2S |
shadowed_reset_glitch |
kmac_shadow_reg_errors |
1.270s |
56.868us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error_with_csr_rw |
kmac_shadow_reg_errors_with_csr_rw |
2.500s |
115.167us |
1 |
1 |
100.00 |
| V2S |
tl_intg_err |
kmac_sec_cm |
1.353m |
8.073ms |
1 |
1 |
100.00 |
|
|
kmac_tl_intg_err |
2.160s |
127.296us |
1 |
1 |
100.00 |
| V2S |
sec_cm_bus_integrity |
kmac_tl_intg_err |
2.160s |
127.296us |
1 |
1 |
100.00 |
| V2S |
sec_cm_lc_escalate_en_intersig_mubi |
kmac_lc_escalation |
1.750s |
50.206us |
1 |
1 |
100.00 |
| V2S |
sec_cm_sw_key_key_masking |
kmac_smoke |
51.930s |
33.770ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_key_sideload |
kmac_sideload |
9.590s |
557.447us |
1 |
1 |
100.00 |
| V2S |
sec_cm_cfg_shadowed_config_shadow |
kmac_shadow_reg_errors |
1.270s |
56.868us |
1 |
1 |
100.00 |
| V2S |
sec_cm_fsm_sparse |
kmac_sec_cm |
1.353m |
8.073ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_ctr_redun |
kmac_sec_cm |
1.353m |
8.073ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_packer_ctr_redun |
kmac_sec_cm |
1.353m |
8.073ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_cfg_shadowed_config_regwen |
kmac_smoke |
51.930s |
33.770ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_fsm_global_esc |
kmac_lc_escalation |
1.750s |
50.206us |
1 |
1 |
100.00 |
| V2S |
sec_cm_fsm_local_esc |
kmac_sec_cm |
1.353m |
8.073ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_absorbed_ctrl_mubi |
kmac_mubi |
15.530s |
1.045ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_sw_cmd_ctrl_sparse |
kmac_smoke |
51.930s |
33.770ms |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
5 |
5 |
100.00 |
| V3 |
stress_all_with_rand_reset |
kmac_stress_all_with_rand_reset |
1.160m |
2.995ms |
1 |
1 |
100.00 |
| V3 |
|
TOTAL |
|
|
1 |
1 |
100.00 |
|
|
TOTAL |
|
|
40 |
40 |
100.00 |