KMAC/UNMASKED Simulation Results

Wednesday November 05 2025 19:20:47 UTC

GitHub Revision: 9baed2b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	12.210s	337.834us	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.140s	185.860us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.270s	68.686us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	14.420s	1.442ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	6.490s	5.401ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.220s	111.925us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.270s	68.686us	1	1	100.00
		kmac_csr_aliasing	6.490s	5.401ms	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.000s	91.443us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.460s	34.256us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	22.199m	444.899ms	1	1	100.00
V2	burst_write	kmac_burst_write	6.381m	14.257ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	26.140s	3.628ms	1	1	100.00
		kmac_test_vectors_sha3_256	27.263m	232.364ms	1	1	100.00
		kmac_test_vectors_sha3_384	13.931m	49.949ms	1	1	100.00
		kmac_test_vectors_sha3_512	14.239m	135.411ms	1	1	100.00
		kmac_test_vectors_shake_128	2.543m	16.344ms	1	1	100.00
		kmac_test_vectors_shake_256	1.603m	7.041ms	1	1	100.00
		kmac_test_vectors_kmac	2.030s	51.540us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.010s	132.316us	1	1	100.00
V2	sideload	kmac_sideload	1.207m	4.653ms	1	1	100.00
V2	app	kmac_app	2.297m	20.688ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	3.173m	37.774ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	3.546m	62.769ms	1	1	100.00
V2	error	kmac_error	52.780s	4.858ms	1	1	100.00
V2	key_error	kmac_key_error	5.550s	2.886ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	24.350s	10.092ms	0	1	0.00
V2	edn_timeout_error	kmac_edn_timeout_error	17.200s	3.994ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	15.610s	1.710ms	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	41.690s	26.560ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	1.750s	42.544us	1	1	100.00
V2	stress_all	kmac_stress_all	2.690m	15.304ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.080s	13.987us	1	1	100.00
V2	alert_test	kmac_alert_test	0.900s	14.197us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.390s	120.237us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.390s	120.237us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.140s	185.860us	1	1	100.00
		kmac_csr_rw	1.270s	68.686us	1	1	100.00
		kmac_csr_aliasing	6.490s	5.401ms	1	1	100.00
		kmac_same_csr_outstanding	1.810s	364.144us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.140s	185.860us	1	1	100.00
		kmac_csr_rw	1.270s	68.686us	1	1	100.00
		kmac_csr_aliasing	6.490s	5.401ms	1	1	100.00
		kmac_same_csr_outstanding	1.810s	364.144us	1	1	100.00
V2		TOTAL			25	26	96.15
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.670s	57.499us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.670s	57.499us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.670s	57.499us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.670s	57.499us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.930s	109.077us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	18.190s	1.543ms	1	1	100.00
		kmac_tl_intg_err	4.290s	236.197us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	4.290s	236.197us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.750s	42.544us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	12.210s	337.834us	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	1.207m	4.653ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.670s	57.499us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	18.190s	1.543ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	18.190s	1.543ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	18.190s	1.543ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	12.210s	337.834us	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.750s	42.544us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	18.190s	1.543ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	1.060m	6.294ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	12.210s	337.834us	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	23.330s	3.040ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			38	40	95.00

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 0.kmac_sideload_invalid.41319910214544840764457653448440158396530920083699792785181823966553382542189
      Line 78, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10091641858 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x6316000, Comparison=CompareOpEq, exp_data=0x1, call_count=4)
        UVM_INFO @ 10091641858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1229) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.50551245261588552970930963383250678414206701789797395262729770411310121912744
      Line 93, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3039704570 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 3039704570 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---