OTBN Simulation Results

Wednesday November 05 2025 19:20:47 UTC

GitHub Revision: 9baed2b

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke otbn_smoke 8.000s 106.841us 0 1 0.00
V1 single_binary otbn_single 15.000s 55.553us 0 1 0.00
V1 csr_hw_reset otbn_csr_hw_reset 5.000s 60.076us 1 1 100.00
V1 csr_rw otbn_csr_rw 3.000s 121.481us 1 1 100.00
V1 csr_bit_bash otbn_csr_bit_bash 5.000s 57.551us 1 1 100.00
V1 csr_aliasing otbn_csr_aliasing 3.000s 71.983us 1 1 100.00
V1 csr_mem_rw_with_rand_reset otbn_csr_mem_rw_with_rand_reset 7.000s 55.948us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr otbn_csr_rw 3.000s 121.481us 1 1 100.00
otbn_csr_aliasing 3.000s 71.983us 1 1 100.00
V1 mem_walk otbn_mem_walk 18.000s 1.952ms 1 1 100.00
V1 mem_partial_access otbn_mem_partial_access 17.000s 1.754ms 1 1 100.00
V1 TOTAL 7 9 77.78
V2 reset_recovery otbn_reset 33.000s 103.620us 0 1 0.00
V2 multi_error otbn_multi_err 31.000s 572.991us 0 1 0.00
V2 back_to_back otbn_multi 57.000s 173.984us 0 1 0.00
V2 stress_all otbn_stress_all 1.050m 1.609ms 0 1 0.00
V2 lc_escalation otbn_escalate 8.000s 38.247us 1 1 100.00
V2 zero_state_err_urnd otbn_zero_state_err_urnd 6.000s 33.944us 1 1 100.00
V2 sw_errs_fatal_chk otbn_sw_errs_fatal_chk 6.000s 83.481us 0 1 0.00
V2 alert_test otbn_alert_test 5.000s 16.067us 1 1 100.00
V2 intr_test otbn_intr_test 4.000s 17.599us 1 1 100.00
V2 tl_d_oob_addr_access otbn_tl_errors 5.000s 177.656us 1 1 100.00
V2 tl_d_illegal_access otbn_tl_errors 5.000s 177.656us 1 1 100.00
V2 tl_d_outstanding_access otbn_csr_hw_reset 5.000s 60.076us 1 1 100.00
otbn_csr_rw 3.000s 121.481us 1 1 100.00
otbn_csr_aliasing 3.000s 71.983us 1 1 100.00
otbn_same_csr_outstanding 4.000s 16.850us 1 1 100.00
V2 tl_d_partial_access otbn_csr_hw_reset 5.000s 60.076us 1 1 100.00
otbn_csr_rw 3.000s 121.481us 1 1 100.00
otbn_csr_aliasing 3.000s 71.983us 1 1 100.00
otbn_same_csr_outstanding 4.000s 16.850us 1 1 100.00
V2 TOTAL 6 11 54.55
V2S mem_integrity otbn_imem_err 9.000s 124.696us 0 1 0.00
otbn_dmem_err 5.000s 45.957us 0 1 0.00
V2S internal_integrity otbn_alu_bignum_mod_err 4.000s 13.047us 0 1 0.00
otbn_controller_ispr_rdata_err 8.000s 29.567us 0 1 0.00
otbn_mac_bignum_acc_err 7.000s 77.578us 0 1 0.00
otbn_urnd_err 5.000s 29.549us 0 1 0.00
V2S illegal_bus_access otbn_illegal_mem_acc 6.000s 62.173us 1 1 100.00
V2S otbn_mem_gnt_acc_err otbn_mem_gnt_acc_err 5.000s 60.227us 1 1 100.00
V2S otbn_non_sec_partial_wipe otbn_partial_wipe 4.000s 48.473us 1 1 100.00
V2S tl_intg_err otbn_sec_cm 10.000s 47.502us 0 1 0.00
otbn_tl_intg_err 15.000s 210.004us 1 1 100.00
V2S passthru_mem_tl_intg_err otbn_passthru_mem_tl_intg_err 12.000s 110.456us 1 1 100.00
V2S prim_fsm_check otbn_sec_cm 10.000s 47.502us 0 1 0.00
V2S prim_count_check otbn_sec_cm 10.000s 47.502us 0 1 0.00
V2S sec_cm_mem_scramble otbn_smoke 8.000s 106.841us 0 1 0.00
V2S sec_cm_data_mem_integrity otbn_dmem_err 5.000s 45.957us 0 1 0.00
V2S sec_cm_instruction_mem_integrity otbn_imem_err 9.000s 124.696us 0 1 0.00
V2S sec_cm_bus_integrity otbn_tl_intg_err 15.000s 210.004us 1 1 100.00
V2S sec_cm_controller_fsm_global_esc otbn_escalate 8.000s 38.247us 1 1 100.00
V2S sec_cm_controller_fsm_local_esc otbn_imem_err 9.000s 124.696us 0 1 0.00
otbn_dmem_err 5.000s 45.957us 0 1 0.00
otbn_zero_state_err_urnd 6.000s 33.944us 1 1 100.00
otbn_illegal_mem_acc 6.000s 62.173us 1 1 100.00
otbn_sec_cm 10.000s 47.502us 0 1 0.00
V2S sec_cm_controller_fsm_sparse otbn_sec_cm 10.000s 47.502us 0 1 0.00
V2S sec_cm_scramble_key_sideload otbn_single 15.000s 55.553us 0 1 0.00
V2S sec_cm_scramble_ctrl_fsm_local_esc otbn_imem_err 9.000s 124.696us 0 1 0.00
otbn_dmem_err 5.000s 45.957us 0 1 0.00
otbn_zero_state_err_urnd 6.000s 33.944us 1 1 100.00
otbn_illegal_mem_acc 6.000s 62.173us 1 1 100.00
otbn_sec_cm 10.000s 47.502us 0 1 0.00
V2S sec_cm_scramble_ctrl_fsm_sparse otbn_sec_cm 10.000s 47.502us 0 1 0.00
V2S sec_cm_start_stop_ctrl_fsm_global_esc otbn_escalate 8.000s 38.247us 1 1 100.00
V2S sec_cm_start_stop_ctrl_fsm_local_esc otbn_imem_err 9.000s 124.696us 0 1 0.00
otbn_dmem_err 5.000s 45.957us 0 1 0.00
otbn_zero_state_err_urnd 6.000s 33.944us 1 1 100.00
otbn_illegal_mem_acc 6.000s 62.173us 1 1 100.00
otbn_sec_cm 10.000s 47.502us 0 1 0.00
V2S sec_cm_start_stop_ctrl_fsm_sparse otbn_sec_cm 10.000s 47.502us 0 1 0.00
V2S sec_cm_data_reg_sw_sca otbn_single 15.000s 55.553us 0 1 0.00
V2S sec_cm_ctrl_redun otbn_ctrl_redun 7.000s 32.994us 0 1 0.00
V2S sec_cm_pc_ctrl_flow_redun otbn_pc_ctrl_flow_redun 7.000s 21.075us 1 1 100.00
V2S sec_cm_rnd_bus_consistency otbn_rnd_sec_cm 40.000s 501.433us 0 1 0.00
V2S sec_cm_rnd_rng_digest otbn_rnd_sec_cm 40.000s 501.433us 0 1 0.00
V2S sec_cm_rf_base_data_reg_sw_integrity otbn_rf_base_intg_err 7.000s 21.480us 0 1 0.00
V2S sec_cm_rf_base_data_reg_sw_glitch_detect otbn_sec_cm 10.000s 47.502us 0 1 0.00
V2S sec_cm_stack_wr_ptr_ctr_redun otbn_sec_cm 10.000s 47.502us 0 1 0.00
V2S sec_cm_rf_bignum_data_reg_sw_integrity otbn_rf_bignum_intg_err 5.000s 51.558us 0 1 0.00
V2S sec_cm_rf_bignum_data_reg_sw_glitch_detect otbn_sec_cm 10.000s 47.502us 0 1 0.00
V2S sec_cm_loop_stack_ctr_redun otbn_sec_cm 10.000s 47.502us 0 1 0.00
V2S sec_cm_loop_stack_addr_integrity otbn_stack_addr_integ_chk 8.000s 42.213us 0 1 0.00
V2S sec_cm_call_stack_addr_integrity otbn_stack_addr_integ_chk 8.000s 42.213us 0 1 0.00
V2S sec_cm_start_stop_ctrl_state_consistency otbn_sec_wipe_err 8.000s 66.952us 0 1 0.00
V2S sec_cm_data_mem_sec_wipe otbn_single 15.000s 55.553us 0 1 0.00
V2S sec_cm_instruction_mem_sec_wipe otbn_single 15.000s 55.553us 0 1 0.00
V2S sec_cm_data_reg_sw_sec_wipe otbn_single 15.000s 55.553us 0 1 0.00
V2S sec_cm_write_mem_integrity otbn_multi 57.000s 173.984us 0 1 0.00
V2S sec_cm_ctrl_flow_count otbn_single 15.000s 55.553us 0 1 0.00
V2S sec_cm_ctrl_flow_sca otbn_single 15.000s 55.553us 0 1 0.00
V2S sec_cm_data_mem_sw_noaccess otbn_sw_no_acc 5.000s 39.015us 0 1 0.00
V2S sec_cm_key_sideload otbn_single 15.000s 55.553us 0 1 0.00
V2S sec_cm_tlul_fifo_ctr_redun otbn_sec_cm 10.000s 47.502us 0 1 0.00
V2S TOTAL 6 20 30.00
V3 stress_all_with_rand_reset otbn_stress_all_with_rand_reset 2.317m 805.946us 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 19 41 46.34

Failure Buckets