PATTGEN Simulation Results

Wednesday November 05 2025 19:20:47 UTC

GitHub Revision: 9baed2b

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	9.000s	413.856us	1	1	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	2.000s	62.827us	1	1	100.00
V1	csr_rw	pattgen_csr_rw	1.000s	15.503us	1	1	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	2.000s	605.645us	1	1	100.00
V1	csr_aliasing	pattgen_csr_aliasing	1.000s	88.349us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	1.000s	24.084us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	1.000s	15.503us	1	1	100.00
		pattgen_csr_aliasing	1.000s	88.349us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	perf	pattgen_perf	14.517m	600.000ms	0	1	0.00
V2	cnt_rollover	cnt_rollover	11.000s	1.363ms	1	1	100.00
V2	error	pattgen_error	7.000s	17.005us	1	1	100.00
V2	stress_all	pattgen_stress_all	1.923h	10.000s	0	1	0.00
V2	alert_test	pattgen_alert_test	2.000s	16.415us	1	1	100.00
V2	intr_test	pattgen_intr_test	2.000s	14.049us	1	1	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	2.000s	44.255us	1	1	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	2.000s	44.255us	1	1	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	2.000s	62.827us	1	1	100.00
		pattgen_csr_rw	1.000s	15.503us	1	1	100.00
		pattgen_csr_aliasing	1.000s	88.349us	1	1	100.00
		pattgen_same_csr_outstanding	2.000s	35.262us	1	1	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	2.000s	62.827us	1	1	100.00
		pattgen_csr_rw	1.000s	15.503us	1	1	100.00
		pattgen_csr_aliasing	1.000s	88.349us	1	1	100.00
		pattgen_same_csr_outstanding	2.000s	35.262us	1	1	100.00
V2		TOTAL			6	8	75.00
V2S	tl_intg_err	pattgen_tl_intg_err	2.000s	182.860us	1	1	100.00
		pattgen_sec_cm	1.000s	244.939us	1	1	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	2.000s	182.860us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	1.367m	5.601ms	0	1	0.00
V3		TOTAL			0	1	0.00
	Unmapped tests	pattgen_inactive_level	2.000s	48.512us	1	1	100.00
		TOTAL			15	18	83.33

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:

  • Test pattgen_perf has 1 failures.

    • 0.pattgen_perf.88018453973064469590368095559933001329124016576332302804261903516687272469438
      Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_perf/latest/run.log

        UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test pattgen_stress_all has 1 failures.

    • 0.pattgen_stress_all.108216248343523976859636502238489612650162835288879442794681704351714055100501
      Line 113, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all/latest/run.log

        UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1230) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test pattgen_stress_all_with_rand_reset has 1 failures.

    • 0.pattgen_stress_all_with_rand_reset.36466183306111058821809996077289605913850316876888035940965064239433859329555
      Line 111, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 197958783 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_ERROR @ 197963168 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 197963168 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
        Issuing reset for run 1/10
        UVM_INFO @ 198025022 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]