ROM_CTRL/32KB Simulation Results

Wednesday November 05 2025 19:20:47 UTC

GitHub Revision: 9baed2b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 3.690s 372.432us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 4.000s 270.587us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 2.980s 556.427us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 4.210s 126.244us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 3.270s 206.481us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 3.230s 804.304us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 2.980s 556.427us 1 1 100.00
rom_ctrl_csr_aliasing 3.270s 206.481us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 3.750s 126.754us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 3.440s 1.161ms 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 4.710s 995.861us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 15.690s 2.705ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 7.410s 1.082ms 1 1 100.00
V2 alert_test rom_ctrl_alert_test 4.660s 167.108us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 6.630s 296.833us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 6.630s 296.833us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 4.000s 270.587us 1 1 100.00
rom_ctrl_csr_rw 2.980s 556.427us 1 1 100.00
rom_ctrl_csr_aliasing 3.270s 206.481us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.620s 299.557us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 4.000s 270.587us 1 1 100.00
rom_ctrl_csr_rw 2.980s 556.427us 1 1 100.00
rom_ctrl_csr_aliasing 3.270s 206.481us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.620s 299.557us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 36.550s 5.420ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 20.940s 3.609ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 1.678m 675.584us 1 1 100.00
rom_ctrl_tl_intg_err 23.340s 419.121us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 1.678m 675.584us 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 1.678m 675.584us 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 36.550s 5.420ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 36.550s 5.420ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 36.550s 5.420ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 36.550s 5.420ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 36.550s 5.420ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 1.678m 675.584us 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 1.678m 675.584us 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 3.690s 372.432us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 3.690s 372.432us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 3.690s 372.432us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 23.340s 419.121us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 36.550s 5.420ms 1 1 100.00
rom_ctrl_kmac_err_chk 7.410s 1.082ms 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 36.550s 5.420ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 36.550s 5.420ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 36.550s 5.420ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 20.940s 3.609ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 1.678m 675.584us 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 2.046m 6.434ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00