ROM_CTRL/64KB Simulation Results

Wednesday November 05 2025 19:20:47 UTC

GitHub Revision: 9baed2b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	7.320s	230.919us	1	1	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	11.330s	216.524us	1	1	100.00
V1	csr_rw	rom_ctrl_csr_rw	7.020s	219.022us	1	1	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	6.180s	367.717us	1	1	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	9.250s	6.183ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	10.430s	1.031ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	7.020s	219.022us	1	1	100.00
		rom_ctrl_csr_aliasing	9.250s	6.183ms	1	1	100.00
V1	mem_walk	rom_ctrl_mem_walk	7.120s	300.102us	1	1	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	8.070s	295.106us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	7.100s	228.441us	1	1	100.00
V2	stress_all	rom_ctrl_stress_all	25.930s	2.781ms	1	1	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	14.220s	2.103ms	1	1	100.00
V2	alert_test	rom_ctrl_alert_test	6.160s	214.066us	1	1	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	7.840s	215.561us	1	1	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	7.840s	215.561us	1	1	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	11.330s	216.524us	1	1	100.00
		rom_ctrl_csr_rw	7.020s	219.022us	1	1	100.00
		rom_ctrl_csr_aliasing	9.250s	6.183ms	1	1	100.00
		rom_ctrl_same_csr_outstanding	7.360s	303.518us	1	1	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	11.330s	216.524us	1	1	100.00
		rom_ctrl_csr_rw	7.020s	219.022us	1	1	100.00
		rom_ctrl_csr_aliasing	9.250s	6.183ms	1	1	100.00
		rom_ctrl_same_csr_outstanding	7.360s	303.518us	1	1	100.00
V2		TOTAL			6	6	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	3.945m	32.031ms	1	1	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	39.700s	1.629ms	1	1	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	4.014m	1.137ms	0	1	0.00
		rom_ctrl_tl_intg_err	51.980s	377.760us	1	1	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	4.014m	1.137ms	0	1	0.00
V2S	prim_count_check	rom_ctrl_sec_cm	4.014m	1.137ms	0	1	0.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.945m	32.031ms	1	1	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.945m	32.031ms	1	1	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	3.945m	32.031ms	1	1	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.945m	32.031ms	1	1	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.945m	32.031ms	1	1	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	4.014m	1.137ms	0	1	0.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	4.014m	1.137ms	0	1	0.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	7.320s	230.919us	1	1	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	7.320s	230.919us	1	1	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	7.320s	230.919us	1	1	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	51.980s	377.760us	1	1	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	3.945m	32.031ms	1	1	100.00
		rom_ctrl_kmac_err_chk	14.220s	2.103ms	1	1	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	3.945m	32.031ms	1	1	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.945m	32.031ms	1	1	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	3.945m	32.031ms	1	1	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	39.700s	1.629ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	4.014m	1.137ms	0	1	0.00
V2S		TOTAL			3	4	75.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	3.472m	22.717ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			18	19	94.74

Failure Buckets

• Offending '(curr_fwd | pend_req[d2h.d_source].pend)' has 1 failures:
  • Test rom_ctrl_sec_cm has 1 failures.

    • 0.rom_ctrl_sec_cm.82009539582517255090562687209374765086722830876600788965603579899089852849746
      Line 162, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log

            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 290: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respOpcode_A: started at 19710571ps failed at 19710571ps
            Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 19710571ps failed at 19710571ps
            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'