RV_TIMER Simulation Results

Wednesday November 05 2025 19:20:47 UTC

GitHub Revision: 9baed2b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	1.030s	129.136us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.650s	59.598us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	0.660s	25.291us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	1.480s	580.743us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.710s	92.885us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	0.680s	25.000us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.660s	25.291us	1	1	100.00
		rv_timer_csr_aliasing	0.710s	92.885us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	0.810s	226.437us	0	1	0.00
V2	disabled	rv_timer_disabled	0.820s	245.834us	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	5.567m	534.068ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	5.567m	534.068ms	1	1	100.00
V2	stress	rv_timer_stress_all	4.170s	1.765ms	1	1	100.00
V2	alert_test	rv_timer_alert_test	0.720s	12.766us	1	1	100.00
V2	intr_test	rv_timer_intr_test	0.720s	13.641us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	1.280s	105.990us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	1.280s	105.990us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.650s	59.598us	1	1	100.00
		rv_timer_csr_rw	0.660s	25.291us	1	1	100.00
		rv_timer_csr_aliasing	0.710s	92.885us	1	1	100.00
		rv_timer_same_csr_outstanding	0.840s	133.058us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.650s	59.598us	1	1	100.00
		rv_timer_csr_rw	0.660s	25.291us	1	1	100.00
		rv_timer_csr_aliasing	0.710s	92.885us	1	1	100.00
		rv_timer_same_csr_outstanding	0.840s	133.058us	1	1	100.00
V2		TOTAL			7	8	87.50
V2S	tl_intg_err	rv_timer_sec_cm	0.980s	196.607us	1	1	100.00
		rv_timer_tl_intg_err	1.060s	244.983us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.060s	244.983us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	min_value	rv_timer_min	0.730s	124.286us	0	1	0.00
V3	max_value	rv_timer_max	0.880s	86.934us	0	1	0.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	29.670s	25.083ms	1	1	100.00
V3		TOTAL			1	3	33.33
		TOTAL			16	19	84.21

Failure Buckets

• UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 2 failures:

  • Test rv_timer_min has 1 failures.

    • 0.rv_timer_min.7210557735203025454785687821450361814493742192137308760962204373344659515076
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_min/latest/run.log

        UVM_FATAL @ 124286176 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xe6001304) == 0x1
        UVM_INFO @ 124286176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rv_timer_random_reset has 1 failures.

    • 0.rv_timer_random_reset.5546054038914421337825436045782707311350352692659758669659617519641452008661
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log

        UVM_FATAL @ 226436683 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xa4a4c504) == 0x1
        UVM_INFO @ 226436683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (rv_timer_scoreboard.sv:250) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) has 1 failures:

  • Test rv_timer_max has 1 failures.

    • 0.rv_timer_max.44839194376414960082613923705623976221425215513064328669136500684488149576827
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log

        UVM_ERROR @  86933922 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
        UVM_INFO @  86933922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---