SPI_DEVICE/1R1W Simulation Results

Wednesday November 05 2025 19:20:47 UTC

GitHub Revision: 9baed2b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	4.510s	658.023us	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	0.840s	14.839us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.140s	35.809us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	9.240s	2.422ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	14.890s	1.135ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.710s	133.868us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.140s	35.809us	1	1	100.00
		spi_device_csr_aliasing	14.890s	1.135ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.660s	12.057us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.120s	31.601us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	0.930s	27.940us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	0.950s	4.741us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	0.720s	3.545us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	1.960s	295.387us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.960s	295.387us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	3.090s	1.270ms	1	1	100.00
		spi_device_tpm_sts_read	0.850s	58.634us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	28.440s	8.100ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	6.840s	11.474ms	1	1	100.00
		spi_device_flash_all	0.800s	13.076us	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	4.760s	6.180ms	1	1	100.00
		spi_device_flash_all	0.800s	13.076us	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	4.760s	6.180ms	1	1	100.00
		spi_device_flash_all	0.800s	13.076us	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	0.800s	13.076us	1	1	100.00
V2	cmd_read_status	spi_device_intercept	5.490s	1.313ms	1	1	100.00
		spi_device_flash_all	0.800s	13.076us	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	5.490s	1.313ms	1	1	100.00
		spi_device_flash_all	0.800s	13.076us	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	5.490s	1.313ms	1	1	100.00
		spi_device_flash_all	0.800s	13.076us	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	5.490s	1.313ms	1	1	100.00
		spi_device_flash_all	0.800s	13.076us	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	5.490s	1.313ms	1	1	100.00
		spi_device_flash_all	0.800s	13.076us	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	1.700s	206.512us	1	1	100.00
V2	mailbox_command	spi_device_mailbox	2.620s	4.694ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.620s	4.694ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.620s	4.694ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	9.930s	3.423ms	1	1	100.00
		spi_device_read_buffer_direct	3.180s	253.868us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.620s	4.694ms	1	1	100.00
		spi_device_flash_all	0.800s	13.076us	1	1	100.00
V2	quad_spi	spi_device_flash_all	0.800s	13.076us	1	1	100.00
V2	dual_spi	spi_device_flash_all	0.800s	13.076us	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	2.430s	85.483us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	2.430s	85.483us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	4.510s	658.023us	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	45.570s	9.393ms	1	1	100.00
V2	stress_all	spi_device_stress_all	3.462m	54.254ms	1	1	100.00
V2	alert_test	spi_device_alert_test	0.740s	37.807us	1	1	100.00
V2	intr_test	spi_device_intr_test	0.820s	44.086us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	1.520s	60.908us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	1.520s	60.908us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	0.840s	14.839us	1	1	100.00
		spi_device_csr_rw	1.140s	35.809us	1	1	100.00
		spi_device_csr_aliasing	14.890s	1.135ms	1	1	100.00
		spi_device_same_csr_outstanding	3.450s	226.530us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	0.840s	14.839us	1	1	100.00
		spi_device_csr_rw	1.140s	35.809us	1	1	100.00
		spi_device_csr_aliasing	14.890s	1.135ms	1	1	100.00
		spi_device_same_csr_outstanding	3.450s	226.530us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	0.860s	44.031us	1	1	100.00
		spi_device_tl_intg_err	8.410s	406.480us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	8.410s	406.480us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	1.158m	18.191ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.112337280073796574920622809608390256268622007934966895697008619173534251244695
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   3990934 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[62])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   3990934 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   3990934 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[958])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.109219778821265850783432570890388890970654598097807381796299525408244600752745
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   1055910 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x5feb4a [10111111110101101001010] vs 0x0 [0])
        UVM_ERROR @   1065910 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x66fd5d [11001101111110101011101] vs 0x0 [0])
        UVM_ERROR @   1107910 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xeaf53e [111010101111010100111110] vs 0x0 [0])
        UVM_ERROR @   1180910 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xa576ce [101001010111011011001110] vs 0x0 [0])
        UVM_ERROR @   1186910 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x9fdca9 [100111111101110010101001] vs 0x0 [0])