SPI_DEVICE/2P Simulation Results

Wednesday November 05 2025 19:20:47 UTC

GitHub Revision: 9baed2b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	1.722m	65.453ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	0.970s	32.538us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	0.960s	58.242us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	14.960s	1.398ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	10.320s	3.818ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.030s	44.006us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	0.960s	58.242us	1	1	100.00
		spi_device_csr_aliasing	10.320s	3.818ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.630s	10.431us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.290s	120.849us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	0.930s	15.061us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.090s	15.386us	1	1	100.00
V2	mem_cfg	spi_device_ram_cfg	0.810s	41.640us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	1.360s	75.158us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.360s	75.158us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	4.550s	2.579ms	1	1	100.00
		spi_device_tpm_sts_read	0.910s	40.701us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	9.350s	2.975ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	6.500s	2.563ms	1	1	100.00
		spi_device_flash_all	17.070s	1.857ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	1.840s	29.970us	1	1	100.00
		spi_device_flash_all	17.070s	1.857ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	1.840s	29.970us	1	1	100.00
		spi_device_flash_all	17.070s	1.857ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	17.070s	1.857ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	3.220s	123.455us	1	1	100.00
		spi_device_flash_all	17.070s	1.857ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	3.220s	123.455us	1	1	100.00
		spi_device_flash_all	17.070s	1.857ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	3.220s	123.455us	1	1	100.00
		spi_device_flash_all	17.070s	1.857ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	3.220s	123.455us	1	1	100.00
		spi_device_flash_all	17.070s	1.857ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	3.220s	123.455us	1	1	100.00
		spi_device_flash_all	17.070s	1.857ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	12.710s	19.626ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	16.940s	3.642ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	16.940s	3.642ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	16.940s	3.642ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	3.500s	1.013ms	1	1	100.00
		spi_device_read_buffer_direct	3.230s	168.808us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	16.940s	3.642ms	1	1	100.00
		spi_device_flash_all	17.070s	1.857ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	17.070s	1.857ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	17.070s	1.857ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	6.200s	700.729us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	6.200s	700.729us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	1.722m	65.453ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	4.264m	197.362ms	1	1	100.00
V2	stress_all	spi_device_stress_all	1.381m	8.061ms	1	1	100.00
V2	alert_test	spi_device_alert_test	0.880s	62.202us	1	1	100.00
V2	intr_test	spi_device_intr_test	0.720s	18.005us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	2.570s	529.531us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	2.570s	529.531us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	0.970s	32.538us	1	1	100.00
		spi_device_csr_rw	0.960s	58.242us	1	1	100.00
		spi_device_csr_aliasing	10.320s	3.818ms	1	1	100.00
		spi_device_same_csr_outstanding	2.670s	125.157us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	0.970s	32.538us	1	1	100.00
		spi_device_csr_rw	0.960s	58.242us	1	1	100.00
		spi_device_csr_aliasing	10.320s	3.818ms	1	1	100.00
		spi_device_same_csr_outstanding	2.670s	125.157us	1	1	100.00
V2		TOTAL			22	22	100.00
V2S	tl_intg_err	spi_device_sec_cm	0.940s	82.790us	1	1	100.00
		spi_device_tl_intg_err	5.550s	694.881us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	5.550s	694.881us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	26.140s	6.056ms	1	1	100.00
		TOTAL			33	33	100.00