SPI_HOST Simulation Results

Wednesday November 05 2025 19:20:47 UTC

GitHub Revision: 9baed2b

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	6.000s	289.459us	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	1.000s	16.467us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	2.000s	67.596us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	2.000s	480.458us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	1.000s	72.235us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	2.000s	58.553us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	2.000s	67.596us	1	1	100.00
		spi_host_csr_aliasing	1.000s	72.235us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	2.000s	17.568us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	2.000s	39.099us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	2.000s	21.412us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	4.000s	291.853us	1	1	100.00
		spi_host_error_cmd	1.000s	42.273us	1	1	100.00
		spi_host_event	7.283m	24.350ms	1	1	100.00
V2	clock_rate	spi_host_speed	2.000s	79.609us	1	1	100.00
V2	speed	spi_host_speed	2.000s	79.609us	1	1	100.00
V2	chip_select_timing	spi_host_speed	2.000s	79.609us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	5.000s	221.287us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	2.000s	279.213us	1	1	100.00
V2	cpol_cpha	spi_host_speed	2.000s	79.609us	1	1	100.00
V2	full_cycle	spi_host_speed	2.000s	79.609us	1	1	100.00
V2	duplex	spi_host_smoke	6.000s	289.459us	1	1	100.00
V2	tx_rx_only	spi_host_smoke	6.000s	289.459us	1	1	100.00
V2	stress_all	spi_host_stress_all	1.000s	59.526us	1	1	100.00
V2	spien	spi_host_spien	6.000s	379.122us	1	1	100.00
V2	stall	spi_host_status_stall	1.583m	6.592ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	2.000s	82.152us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	4.000s	291.853us	1	1	100.00
V2	alert_test	spi_host_alert_test	1.000s	17.327us	1	1	100.00
V2	intr_test	spi_host_intr_test	1.000s	37.466us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	2.000s	22.048us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	2.000s	22.048us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	1.000s	16.467us	1	1	100.00
		spi_host_csr_rw	2.000s	67.596us	1	1	100.00
		spi_host_csr_aliasing	1.000s	72.235us	1	1	100.00
		spi_host_same_csr_outstanding	1.000s	283.400us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	1.000s	16.467us	1	1	100.00
		spi_host_csr_rw	2.000s	67.596us	1	1	100.00
		spi_host_csr_aliasing	1.000s	72.235us	1	1	100.00
		spi_host_same_csr_outstanding	1.000s	283.400us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	2.000s	94.909us	1	1	100.00
		spi_host_sec_cm	1.000s	44.592us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	2.000s	94.909us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	6.100m	200.000ms	0	1	0.00
		TOTAL			25	26	96.15

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test spi_host_upper_range_clkdiv has 1 failures.

    • 0.spi_host_upper_range_clkdiv.73588414030220297408271886541690333532286289328373178679725196093537534253092
      Line 112, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/0.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---