SRAM_CTRL/MAIN Simulation Results

Wednesday November 05 2025 19:20:47 UTC

GitHub Revision: 9baed2b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	16.370s	4.208ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.840s	51.982us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.970s	46.516us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.720s	251.704us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.030s	19.371us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	4.340s	4.881ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.970s	46.516us	1	1	100.00
		sram_ctrl_csr_aliasing	1.030s	19.371us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	1.743m	10.526ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.071m	44.729ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	7.271m	28.010ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.653m	19.834ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	8.448m	42.913ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	6.465m	41.081ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	1.133m	54.206ms	1	1	100.00
V2	executable	sram_ctrl_executable	11.652m	21.430ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	13.760s	1.168ms	1	1	100.00
		sram_ctrl_partial_access_b2b	4.025m	12.624ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	58.430s	1.591ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	18.760s	1.528ms	1	1	100.00
		sram_ctrl_throughput_w_readback	50.600s	4.985ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	3.376m	8.334ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	2.780s	690.368us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	1.128h	474.267ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.980s	34.956us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.380s	80.184us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.380s	80.184us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.840s	51.982us	1	1	100.00
		sram_ctrl_csr_rw	0.970s	46.516us	1	1	100.00
		sram_ctrl_csr_aliasing	1.030s	19.371us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.800s	76.024us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.840s	51.982us	1	1	100.00
		sram_ctrl_csr_rw	0.970s	46.516us	1	1	100.00
		sram_ctrl_csr_aliasing	1.030s	19.371us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.800s	76.024us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	54.410s	117.606ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.090s	20.416us	0	1	0.00
		sram_ctrl_tl_intg_err	2.190s	588.963us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.090s	20.416us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.190s	588.963us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	3.376m	8.334ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	3.376m	8.334ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.970s	46.516us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	11.652m	21.430ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	11.652m	21.430ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	11.652m	21.430ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	1.133m	54.206ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	5.500s	6.650ms	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	54.410s	117.606ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	5.720s	667.276us	0	1	0.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	16.370s	4.208ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	16.370s	4.208ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	11.652m	21.430ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.090s	20.416us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	1.133m	54.206ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.090s	20.416us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.090s	20.416us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	16.370s	4.208ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.090s	20.416us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	18.290s	4.460ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 1 failures:

  • Test sram_ctrl_readback_err has 1 failures.

    • 0.sram_ctrl_readback_err.25337201289097979425336979499898737702330642384916066110732801363752066181118
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 667275631 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x7a) != exp (0x4c)
        UVM_INFO @ 667275631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.32045062267989062794436622876464559165815914922461415133733532718983281968885
      Line 100, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  20415632 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  20415632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---