SRAM_CTRL/RET Simulation Results

Wednesday November 05 2025 19:20:47 UTC

GitHub Revision: 9baed2b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.760s	155.219us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.910s	17.562us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.850s	43.124us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.780s	367.194us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.050s	29.166us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	1.630s	34.624us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.850s	43.124us	1	1	100.00
		sram_ctrl_csr_aliasing	1.050s	29.166us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	6.900s	266.526us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.880s	112.311us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	3.010m	7.850ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.439m	8.701ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	24.100s	1.964ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	14.892m	15.264ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	6.330s	1.593ms	1	1	100.00
V2	executable	sram_ctrl_executable	3.566m	23.066ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	46.130s	295.988us	1	1	100.00
		sram_ctrl_partial_access_b2b	9.112m	158.731ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.640s	77.876us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	1.140s	33.316us	1	1	100.00
		sram_ctrl_throughput_w_readback	22.820s	234.258us	1	1	100.00
V2	regwen	sram_ctrl_regwen	8.054m	25.027ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.020s	47.876us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	2.875m	4.116ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.810s	77.478us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.690s	555.999us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.690s	555.999us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.910s	17.562us	1	1	100.00
		sram_ctrl_csr_rw	0.850s	43.124us	1	1	100.00
		sram_ctrl_csr_aliasing	1.050s	29.166us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.050s	97.077us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.910s	17.562us	1	1	100.00
		sram_ctrl_csr_rw	0.850s	43.124us	1	1	100.00
		sram_ctrl_csr_aliasing	1.050s	29.166us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.050s	97.077us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	2.680s	1.564ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.790s	1.609us	0	1	0.00
		sram_ctrl_tl_intg_err	2.020s	253.823us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.790s	1.609us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.020s	253.823us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	8.054m	25.027ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	8.054m	25.027ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.850s	43.124us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	3.566m	23.066ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	3.566m	23.066ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	3.566m	23.066ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	6.330s	1.593ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.030s	43.543us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	2.680s	1.564ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.280s	34.925us	0	1	0.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.760s	155.219us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.760s	155.219us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	3.566m	23.066ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.790s	1.609us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	6.330s	1.593ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.790s	1.609us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.790s	1.609us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.760s	155.219us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.790s	1.609us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	59.140s	1.608ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 1 failures:

  • Test sram_ctrl_readback_err has 1 failures.

    • 0.sram_ctrl_readback_err.33697656719218652780731057176483471882420701256174148263359754204360558211710
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @  34924722 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x6e) != exp (0x7a)
        UVM_INFO @  34924722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(curr_fwd | pend_req[d2h.d_source].pend)' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.45869903603164191635888258316186262513678111510558572197407192868044839284468
      Line 98, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        UVM_ERROR @   1608544 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   1608544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---