SYSRST_CTRL Simulation Results

Wednesday November 05 2025 19:20:47 UTC

GitHub Revision: 9baed2b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sysrst_ctrl_smoke 5.800s 2.111ms 1 1 100.00
V1 input_output_inverted sysrst_ctrl_in_out_inverted 4.020s 2.456ms 1 1 100.00
V1 combo_detect_ec_rst sysrst_ctrl_combo_detect_ec_rst 5.190s 2.200ms 1 1 100.00
V1 combo_detect_ec_rst_with_pre_cond sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 1.850s 2.287ms 1 1 100.00
V1 csr_hw_reset sysrst_ctrl_csr_hw_reset 15.060s 6.031ms 1 1 100.00
V1 csr_rw sysrst_ctrl_csr_rw 2.140s 2.122ms 1 1 100.00
V1 csr_bit_bash sysrst_ctrl_csr_bit_bash 21.160s 38.169ms 1 1 100.00
V1 csr_aliasing sysrst_ctrl_csr_aliasing 9.200s 3.126ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset sysrst_ctrl_csr_mem_rw_with_rand_reset 2.000s 2.160ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr sysrst_ctrl_csr_rw 2.140s 2.122ms 1 1 100.00
sysrst_ctrl_csr_aliasing 9.200s 3.126ms 1 1 100.00
V1 TOTAL 9 9 100.00
V2 combo_detect sysrst_ctrl_combo_detect 56.110s 129.599ms 1 1 100.00
V2 combo_detect_with_pre_cond sysrst_ctrl_combo_detect_with_pre_cond 15.610s 30.112ms 1 1 100.00
V2 auto_block_key_outputs sysrst_ctrl_auto_blk_key_output 7.180s 3.299ms 1 1 100.00
V2 keyboard_input_triggered_interrupt sysrst_ctrl_edge_detect 4.750s 2.403ms 1 1 100.00
V2 pin_output_keyboard_inversion_control sysrst_ctrl_pin_override_test 2.250s 2.531ms 1 1 100.00
V2 pin_input_value_accessibility sysrst_ctrl_pin_access_test 4.050s 2.152ms 1 1 100.00
V2 ec_power_on_reset sysrst_ctrl_ec_pwr_on_rst 4.223m 348.930ms 1 1 100.00
V2 flash_write_protect_output sysrst_ctrl_flash_wr_prot_out 7.120s 2.612ms 1 1 100.00
V2 ultra_low_power_test sysrst_ctrl_ultra_low_pwr 1.680s 6.957ms 1 1 100.00
V2 sysrst_ctrl_feature_disable sysrst_ctrl_feature_disable 20.390s 38.776ms 1 1 100.00
V2 stress_all sysrst_ctrl_stress_all 8.490s 8.617ms 1 1 100.00
V2 alert_test sysrst_ctrl_alert_test 8.140s 2.014ms 1 1 100.00
V2 intr_test sysrst_ctrl_intr_test 4.880s 2.010ms 1 1 100.00
V2 tl_d_oob_addr_access sysrst_ctrl_tl_errors 3.830s 2.135ms 1 1 100.00
V2 tl_d_illegal_access sysrst_ctrl_tl_errors 3.830s 2.135ms 1 1 100.00
V2 tl_d_outstanding_access sysrst_ctrl_csr_hw_reset 15.060s 6.031ms 1 1 100.00
sysrst_ctrl_csr_rw 2.140s 2.122ms 1 1 100.00
sysrst_ctrl_csr_aliasing 9.200s 3.126ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 3.330s 7.886ms 1 1 100.00
V2 tl_d_partial_access sysrst_ctrl_csr_hw_reset 15.060s 6.031ms 1 1 100.00
sysrst_ctrl_csr_rw 2.140s 2.122ms 1 1 100.00
sysrst_ctrl_csr_aliasing 9.200s 3.126ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 3.330s 7.886ms 1 1 100.00
V2 TOTAL 15 15 100.00
V2S tl_intg_err sysrst_ctrl_sec_cm 23.060s 42.123ms 1 1 100.00
sysrst_ctrl_tl_intg_err 49.370s 22.262ms 1 1 100.00
V2S sec_cm_bus_integrity sysrst_ctrl_tl_intg_err 49.370s 22.262ms 1 1 100.00
V2S TOTAL 2 2 100.00
V3 stress_all_with_rand_reset sysrst_ctrl_stress_all_with_rand_reset 12.030s 19.132ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 27 27 100.00