UART Simulation Results

Wednesday November 05 2025 19:20:47 UTC

GitHub Revision: 9baed2b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	6.780s	5.647ms	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.680s	65.065us	1	1	100.00
V1	csr_rw	uart_csr_rw	0.760s	15.870us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.250s	364.229us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	0.780s	47.998us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	0.710s	78.154us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.760s	15.870us	1	1	100.00
		uart_csr_aliasing	0.780s	47.998us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	5.260s	4.498ms	1	1	100.00
V2	parity	uart_smoke	6.780s	5.647ms	1	1	100.00
		uart_tx_rx	5.260s	4.498ms	1	1	100.00
V2	parity_error	uart_intr	36.730s	35.108ms	1	1	100.00
		uart_rx_parity_err	1.924m	97.029ms	1	1	100.00
V2	watermark	uart_tx_rx	5.260s	4.498ms	1	1	100.00
		uart_intr	36.730s	35.108ms	1	1	100.00
V2	fifo_full	uart_fifo_full	39.470s	354.303ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	1.985m	113.258ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	6.642m	174.864ms	1	1	100.00
V2	rx_frame_err	uart_intr	36.730s	35.108ms	1	1	100.00
V2	rx_break_err	uart_intr	36.730s	35.108ms	1	1	100.00
V2	rx_timeout	uart_intr	36.730s	35.108ms	1	1	100.00
V2	perf	uart_perf	13.046m	18.598ms	1	1	100.00
V2	sys_loopback	uart_loopback	11.140s	8.277ms	1	1	100.00
V2	line_loopback	uart_loopback	11.140s	8.277ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	1.930s	1.139ms	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	28.510s	23.679ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	1.410s	430.512us	1	1	100.00
V2	rx_oversample	uart_rx_oversample	25.880s	4.510ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	8.937m	150.817ms	1	1	100.00
V2	stress_all	uart_stress_all	34.080s	59.104ms	0	1	0.00
V2	alert_test	uart_alert_test	0.600s	203.041us	1	1	100.00
V2	intr_test	uart_intr_test	0.590s	13.143us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.740s	800.778us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.740s	800.778us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.680s	65.065us	1	1	100.00
		uart_csr_rw	0.760s	15.870us	1	1	100.00
		uart_csr_aliasing	0.780s	47.998us	1	1	100.00
		uart_same_csr_outstanding	0.870s	51.620us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.680s	65.065us	1	1	100.00
		uart_csr_rw	0.760s	15.870us	1	1	100.00
		uart_csr_aliasing	0.780s	47.998us	1	1	100.00
		uart_same_csr_outstanding	0.870s	51.620us	1	1	100.00
V2		TOTAL			16	18	88.89
V2S	tl_intg_err	uart_sec_cm	1.060s	41.664us	1	1	100.00
		uart_tl_intg_err	1.270s	591.659us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.270s	591.659us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	16.910s	9.644ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			25	27	92.59

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * has 2 failures:

  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.57384868732655037405302545856429574033355969760467193251171826182508235538530
      Line 71, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @ 354437927 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2,                                 clk_pulses: 0
        UVM_ERROR @ 354465705 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 354493483 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata
        UVM_ERROR @ 354521261 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 354549039 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata
      

  • Test uart_stress_all has 1 failures.

    • 0.uart_stress_all.108468587226639812550552890118172609160895745437795075760389400740070260867843
      Line 98, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_stress_all/latest/run.log

        UVM_ERROR @ 56598848303 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2,                                 clk_pulses: 0
        UVM_ERROR @ 56598869136 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 56598889969 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (67 [0x43] vs 255 [0xff]) reg name: uart_reg_block.rdata
        UVM_ERROR @ 56598910802 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 56598931635 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (67 [0x43] vs 254 [0xfe]) reg name: uart_reg_block.rdata