CHIP Simulation Results

Wednesday November 05 2025 19:20:47 UTC

GitHub Revision: `9baed2b`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	2.214m	2.603ms	1	1	100.00
		chip_sw_example_rom	57.330s	1.978ms	1	1	100.00
		chip_sw_example_manufacturer	1.896m	2.539ms	1	1	100.00
		chip_sw_example_concurrency	2.732m	2.384ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	3.491m	7.445ms	1	1	100.00
V1	csr_rw	chip_csr_rw	3.289m	4.186ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	4.990m	5.626ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	1.108h	36.113ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	3.832m	6.250ms	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	1.108h	36.113ms	1	1	100.00
		chip_csr_rw	3.289m	4.186ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	4.440s	44.900us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	4.541m	4.185ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	4.541m	4.185ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	4.541m	4.185ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	5.716m	4.299ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	5.716m	4.299ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	6.025m	4.955ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	5.691m	4.104ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	6.021m	3.892ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	16.667m	8.191ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	18.200m	8.302ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	4.616m	4.537ms	1	1	100.00
V1		TOTAL			17	18	94.44
V2	chip_pin_mux	chip_padctrl_attributes	2.494m	4.835ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	2.494m	4.835ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	3.084m	2.679ms	1	1	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.656m	3.555ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.425m	3.488ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	12.458m	11.946ms	1	1	100.00
		chip_tap_straps_testunlock0	1.555m	2.417ms	1	1	100.00
		chip_tap_straps_rma	7.614m	6.969ms	1	1	100.00
		chip_tap_straps_prod	1.747m	2.659ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	2.562m	3.347ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	13.083m	8.336ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	5.299m	4.591ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	5.299m	4.591ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	10.788m	8.070ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	23.556m	15.222ms	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	6.520m	4.532ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	10.112m	5.775ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	54.837m	18.255ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.322m	3.101ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	8.043m	5.443ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	1.820m	2.148ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	10.412m	6.599ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.872m	3.361ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.624m	4.613ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.525m	3.653ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	3.137m	2.762ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	5.313m	4.537ms	0	1	0.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.155m	5.230ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	1.814m	3.045ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.155m	5.230ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	2.791m	3.157ms	1	1	100.00
		chip_sw_aes_smoketest	2.204m	2.594ms	1	1	100.00
		chip_sw_aon_timer_smoketest	2.612m	2.507ms	1	1	100.00
		chip_sw_clkmgr_smoketest	2.331m	3.069ms	1	1	100.00
		chip_sw_csrng_smoketest	2.566m	3.234ms	1	1	100.00
		chip_sw_entropy_src_smoketest	14.792m	7.555ms	1	1	100.00
		chip_sw_gpio_smoketest	2.464m	2.428ms	1	1	100.00
		chip_sw_hmac_smoketest	2.585m	2.458ms	1	1	100.00
		chip_sw_kmac_smoketest	2.873m	3.233ms	1	1	100.00
		chip_sw_otbn_smoketest	10.888m	5.989ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	3.336m	5.775ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	4.100m	5.746ms	1	1	100.00
		chip_sw_rv_plic_smoketest	1.828m	2.747ms	1	1	100.00
		chip_sw_rv_timer_smoketest	2.495m	2.853ms	1	1	100.00
		chip_sw_rstmgr_smoketest	2.010m	2.294ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	2.638m	3.354ms	1	1	100.00
		chip_sw_uart_smoketest	2.446m	2.304ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	2.450m	2.641ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	4.264m	3.647ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	2.089h	63.356ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	41.083m	15.943ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	11.861m	16.313ms	0	1	0.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	3.319m	3.583ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	3.691m	3.412ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	2.021h	54.198ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	2.104h	56.890ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	42.820s	2.011ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	42.820s	2.011ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	1.108h	36.113ms	1	1	100.00
		chip_same_csr_outstanding	26.363m	16.259ms	1	1	100.00
		chip_csr_hw_reset	3.491m	7.445ms	1	1	100.00
		chip_csr_rw	3.289m	4.186ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	1.108h	36.113ms	1	1	100.00
		chip_same_csr_outstanding	26.363m	16.259ms	1	1	100.00
		chip_csr_hw_reset	3.491m	7.445ms	1	1	100.00
		chip_csr_rw	3.289m	4.186ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	5.970s	63.399us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	4.510s	47.753us	1	1	100.00
		xbar_smoke_large_delays	1.069m	9.975ms	1	1	100.00
		xbar_smoke_slow_rsp	40.050s	4.626ms	1	1	100.00
		xbar_random_zero_delays	32.130s	621.525us	1	1	100.00
		xbar_random_large_delays	1.796m	17.905ms	1	1	100.00
		xbar_random_slow_rsp	4.209m	29.713ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	18.680s	603.785us	1	1	100.00
		xbar_error_and_unmapped_addr	24.460s	1.186ms	1	1	100.00
V2	xbar_error_cases	xbar_error_random	13.340s	402.248us	1	1	100.00
		xbar_error_and_unmapped_addr	24.460s	1.186ms	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	30.720s	1.232ms	1	1	100.00
		xbar_access_same_device_slow_rsp	4.817m	32.998ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	16.740s	839.887us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	2.782m	7.273ms	1	1	100.00
		xbar_stress_all_with_error	1.629m	4.395ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	1.172m	267.685us	1	1	100.00
		xbar_stress_all_with_reset_error	13.940s	147.139us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	41.083m	15.943ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	40.232m	29.710ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	43.748m	15.913ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	36.047m	13.433ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	44.957m	17.278ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	44.766m	16.163ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	40.812m	15.720ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	42.415m	16.212ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	20.970s	10.120us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	19.840s	10.120us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	23.470s	10.160us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	25.210s	10.240us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	23.530s	10.280us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	18.690s	10.180us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	18.110s	10.140us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	17.300s	10.280us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	22.320s	10.100us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	27.680s	10.180us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	16.550s	10.160us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	17.210s	10.280us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	17.810s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	17.020s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	18.180s	10.220us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	17.300s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	22.940s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	20.980s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	18.600s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	20.200s	10.320us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	16.940s	10.120us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	16.400s	10.400us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	17.860s	10.400us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	16.270s	10.400us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	17.040s	10.100us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	31.941m	12.711ms	1	1	100.00
		rom_e2e_asm_init_dev	40.798m	17.168ms	1	1	100.00
		rom_e2e_asm_init_prod	42.023m	16.010ms	1	1	100.00
		rom_e2e_asm_init_prod_end	40.260m	15.417ms	1	1	100.00
		rom_e2e_asm_init_rma	40.502m	15.385ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	39.950m	16.312ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	39.765m	17.266ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	38.979m	15.198ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	42.880m	18.688ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	54.074m	34.563ms	0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	54.074m	34.563ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	3.055m	2.860ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.322m	3.101ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	2.152m	2.621ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	3.089m	3.007ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	18.009m	9.071ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	2.323m	2.919ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	5.327m	6.091ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	6.566m	5.469ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	8.881m	5.405ms	1	1	100.00
		chip_plic_all_irqs_10	3.781m	3.965ms	1	1	100.00
		chip_plic_all_irqs_20	6.615m	4.291ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	2.415m	3.303ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	16.140m	12.608ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	3.920m	4.378ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	2.051m	2.643ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings			0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	13.357m	6.105ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	16.819m	7.615ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	14.174m	7.573ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	2.339h	255.182ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	3.086m	3.452ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	3.336m	5.775ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	3.086m	3.452ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	7.312m	7.544ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	7.312m	7.544ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	4.611m	6.531ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	6.865m	6.432ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	9.649m	5.916ms	1	1	100.00
		chip_sw_aes_idle	3.089m	3.007ms	1	1	100.00
		chip_sw_hmac_enc_idle	2.045m	2.850ms	1	1	100.00
		chip_sw_kmac_idle	2.919m	2.471ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	3.845m	3.740ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	4.321m	4.064ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	3.982m	4.803ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	4.811m	4.725ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	14.254m	12.242ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	6.426m	4.186ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	6.376m	5.027ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.892m	4.332ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.212m	4.557ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	6.898m	4.939ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.874m	3.986ms	1	1	100.00
		chip_sw_ast_clk_outputs	10.788m	8.070ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	6.698m	7.748ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.892m	4.332ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.212m	4.557ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	6.520m	4.532ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	10.112m	5.775ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	54.837m	18.255ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.322m	3.101ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	8.043m	5.443ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	1.820m	2.148ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	10.412m	6.599ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.872m	3.361ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.624m	4.613ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.525m	3.653ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	2.700m	3.269ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	6.525m	4.887ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	11.047m	7.034ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	51.802m	24.992ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	2.538m	3.458ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.685m	2.339ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	21.193m	13.393ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	3.048m	3.607ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	4.985m	4.343ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	20.164m	25.746ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	2.851h	127.570ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	10.788m	8.070ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	6.045m	5.017ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	3.734m	3.399ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	6.566m	5.469ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	13.357m	6.105ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	14.961m	7.643ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	2.344m	2.821ms	0	1	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	7.550m	7.006ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	2.254m	2.679ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	33.392m	12.312ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	2.335m	2.865ms	1	1	100.00
		chip_sw_edn_entropy_reqs	13.808m	8.267ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	2.335m	2.865ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	14.961m	7.643ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	2.302m	3.485ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	24.216m	22.207ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	9.588m	4.975ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	10.112m	5.775ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	5.789m	4.003ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	6.520m	4.532ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	54.107m	42.151ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	24.216m	22.207ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	3.091m	2.630ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	16.767m	7.886ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.974m	5.402ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	54.107m	42.151ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.974m	5.402ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.974m	5.402ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	4.974m	5.402ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.974m	5.402ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	6.566m	5.469ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	2.884m	7.205ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	9.619m	4.825ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	5.364m	5.059ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	5.364m	5.059ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	2.717m	2.690ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	1.820m	2.148ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	2.045m	2.850ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	2.141m	2.765ms	0	1	0.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	5.981m	3.281ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	5.978m	5.313ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	6.872m	4.723ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	7.337m	5.404ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	5.598m	4.086ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	16.767m	7.886ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	10.412m	6.599ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	23.429m	10.821ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	18.009m	9.071ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	41.908m	14.727ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	2.940m	3.497ms	1	1	100.00
		chip_sw_kmac_mode_kmac	3.140m	3.127ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.872m	3.361ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	16.767m	7.886ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	6.065m	6.386ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	2.001m	2.165ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	14.338m	6.433ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	2.919m	2.471ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	5.327m	6.091ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	12.458m	11.946ms	1	1	100.00
		chip_tap_straps_rma	7.614m	6.969ms	1	1	100.00
		chip_tap_straps_prod	1.747m	2.659ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.344m	2.303ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	6.065m	6.386ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	6.065m	6.386ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	6.065m	6.386ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	20.057m	9.793ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	4.974m	5.402ms	1	1	100.00
		chip_sw_flash_rma_unlocked	54.107m	42.151ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.117m	3.118ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	9.267m	6.063ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	8.309m	6.729ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	6.913m	7.251ms	0	1	0.00
		chip_sw_lc_ctrl_transition	6.065m	6.386ms	1	1	100.00
		chip_sw_keymgr_key_derivation	16.767m	7.886ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	5.755m	9.536ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	8.610m	7.708ms	1	1	100.00
		chip_prim_tl_access	2.884m	7.205ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	6.698m	7.748ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	6.426m	4.186ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	6.376m	5.027ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.892m	4.332ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.212m	4.557ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	6.898m	4.939ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.874m	3.986ms	1	1	100.00
		chip_tap_straps_dev	12.458m	11.946ms	1	1	100.00
		chip_tap_straps_rma	7.614m	6.969ms	1	1	100.00
		chip_tap_straps_prod	1.747m	2.659ms	1	1	100.00
		chip_rv_dm_lc_disabled	4.579m	9.492ms	1	1	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	1.985m	3.515ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.628m	3.649ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.191m	3.052ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	3.274m	3.678ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	20.280m	23.155ms	1	1	100.00
		chip_rv_dm_lc_disabled	4.579m	9.492ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.028h	49.043ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	1.112h	48.340ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	8.624m	11.213ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	1.048h	45.614ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	20.280m	23.155ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	55.360s	2.056ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.010m	2.175ms	1	1	100.00
		rom_volatile_raw_unlock	1.013m	1.861ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	57.481m	17.518ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	54.837m	18.255ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	9.649m	5.916ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	9.649m	5.916ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	9.649m	5.916ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	4.705m	3.618ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	6.065m	6.386ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	24.216m	22.207ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.705m	3.618ms	1	1	100.00
		chip_sw_keymgr_key_derivation	16.767m	7.886ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	5.015m	4.001ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.530m	2.474ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	24.216m	22.207ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.705m	3.618ms	1	1	100.00
		chip_sw_keymgr_key_derivation	16.767m	7.886ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	5.015m	4.001ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.530m	2.474ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	6.065m	6.386ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	5.433m	5.368ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.344m	2.303ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.117m	3.118ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	9.267m	6.063ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	8.309m	6.729ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	6.913m	7.251ms	0	1	0.00
		chip_sw_lc_ctrl_transition	6.065m	6.386ms	1	1	100.00
		chip_prim_tl_access	2.884m	7.205ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	2.884m	7.205ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	18.453m	9.185ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	4.921m	8.234ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	19.435m	27.731ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	4.335m	7.371ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	4.403m	6.951ms	0	1	0.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	7.852m	7.334ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	14.875m	22.350ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	3.966m	5.341ms	0	1	0.00
		chip_sw_aon_timer_wdog_bite_reset	7.312m	7.544ms	0	1	0.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	11.639m	10.686ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	5.717m	5.212ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	4.921m	8.234ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	3.916m	4.829ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	11.449m	12.935ms	0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	4.338m	5.782ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	4.230m	4.682ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	3.257m	5.931ms	0	1	0.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	11.853m	9.044ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	13.063m	8.960ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	19.891m	23.166ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	3.267m	3.171ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	6.566m	5.469ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	5.755m	9.536ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	5.755m	9.536ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	13.063m	8.960ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	3.257m	5.931ms	0	1	0.00
		chip_sw_pwrmgr_wdog_reset	5.717m	5.212ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	3.336m	5.775ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	3.766m	3.252ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	5.029m	4.552ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	4.242m	4.099ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	16.140m	12.608ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	2.475m	2.843ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	6.566m	5.469ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	16.819m	7.615ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	9.192m	5.013ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	7.482m	5.142ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	2.323m	2.614ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	2.530m	2.474ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	5.029m	4.552ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	5.029m	4.552ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	13.525m	12.818ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	14.595m	13.151ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	3.766m	3.252ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	5.574m	4.611ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	4.136m	5.175ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	7.614m	6.969ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	4.579m	9.492ms	1	1	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	8.881m	5.405ms	1	1	100.00
		chip_plic_all_irqs_10	3.781m	3.965ms	1	1	100.00
		chip_plic_all_irqs_20	6.615m	4.291ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	2.213m	2.837ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	2.629m	3.276ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	41.083m	15.943ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	8.412m	7.634ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	2.971m	2.432ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	2.417m	2.517ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	2.433m	3.038ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	5.015m	4.001ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.624m	4.613ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	7.304m	7.553ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	7.646m	8.513ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	8.610m	7.708ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	6.566m	5.469ms	1	1	100.00
		chip_sw_data_integrity_escalation	5.299m	4.591ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	11.853m	9.044ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	16.951m	23.465ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	1.753m	2.541ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	3.166m	3.125ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	5.560m	4.007ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	16.951m	23.465ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	16.951m	23.465ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	40.399m	20.275ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	40.399m	20.275ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	5.537m	6.693ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	54.074m	34.563ms	0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	2.469m	2.882ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	1.903m	2.561ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	5.217m	3.686ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	5.204m	4.238ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	18.601m	7.984ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.403h	30.916ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	32.135m	12.075ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	1.700m	2.734ms	1	1	100.00
V2		TOTAL			230	275	83.64
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	2.390m	2.663ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	1.646m	2.181ms	0	1	0.00
V2S		TOTAL			1	2	50.00
V3	chip_sw_coremark	chip_sw_coremark	2.571h	71.611ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	17.248m	6.933ms	1	1	100.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	20.696m	10.842ms	1	1	100.00
		rom_e2e_jtag_debug_dev	8.635m	14.819ms	0	1	0.00
		rom_e2e_jtag_debug_rma	18.884m	11.964ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	2.927m	3.973ms	1	1	100.00
		rom_e2e_jtag_inject_dev	4.245m	4.930ms	1	1	100.00
		rom_e2e_jtag_inject_rma	3.670m	4.953ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	13.465s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	9.400m	5.507ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	4.881m	3.302ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	21.115m	7.559ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	13.569m	6.035ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.785m	2.583ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	9.768m	5.254ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	2.380m	2.667ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	2.713m	2.939ms	0	1	0.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	3.478m	4.968ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	3.660m	4.507ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	13.063m	8.960ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	20.696m	10.842ms	1	1	100.00
		rom_e2e_jtag_debug_dev	8.635m	14.819ms	0	1	0.00
		rom_e2e_jtag_debug_rma	18.884m	11.964ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	6.460m	5.629ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	6.566m	5.469ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.581h	38.550ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.581h	38.550ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	3.377m	4.126ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	5.716m	4.299ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	53.168m	19.093ms	1	1	100.00
V3		TOTAL			20	23	86.96
	Unmapped tests	chip_sival_flash_info_access	2.862m	2.475ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	7.200m	4.933ms	1	1	100.00
		chip_sw_otp_ctrl_rot_auth_config	32.554m	31.721ms	0	1	0.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	2.395m	2.775ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	2.416m	2.442ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	4.244m	3.573ms	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	8.572s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	2.454m	2.756ms	1	1	100.00
		TOTAL			274	326	84.05

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.79713432588504845382518245395794500217084953858767273432081514021746847667304
    Line 497, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.85035178295144199083708898641531771981063410626292253576841260926586038953354
    Line 488, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.28192580964303183757454234492518241963346158428789160901513534348424785694006
    Line 507, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.42136017163086860591663008241986570267808577608225876423406462551244753911920
    Line 510, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.98625879985807054934134376280213086275162329428485881889567839098232812545385
    Line 523, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
Offending '(rstreqs[*] && (reset_cause == HwReq))' has 5 failures:
- Test chip_sw_pwrmgr_random_sleep_all_reset_reqs has 1 failures.
  - 0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.19735049191832895963076097802720659874272469384530839309442628673852900026233
    Line 398, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest/run.log
```
      Offending '(rstreqs[0] && (reset_cause == HwReq))'
  UVM_ERROR @ 5931.020000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
  UVM_INFO @ 5931.020000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_pwrmgr_deep_sleep_all_reset_reqs has 1 failures.
  - 0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.117264440266739430128734251642313183241632515069704091836020011722183097088
    Line 397, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest/run.log
```
      Offending '(rstreqs[0] && (reset_cause == HwReq))'
  UVM_ERROR @ 5341.181500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
  UVM_INFO @ 5341.181500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_pwrmgr_deep_sleep_por_reset has 1 failures.
  - 0.chip_sw_pwrmgr_deep_sleep_por_reset.10464033960446064147595625257436084102050355499047235115852319523145112554640
    Line 406, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_por_reset/latest/run.log
```
      Offending '(rstreqs[0] && (reset_cause == HwReq))'
  UVM_ERROR @ 6950.514000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
  UVM_INFO @ 6950.514000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_pwrmgr_random_sleep_power_glitch_reset has 1 failures.
  - 0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.5990403093645990166531170996061236564495432140555339480257835136435727525415
    Line 422, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest/run.log
```
      Offending '(rstreqs[1] && (reset_cause == HwReq))'
  UVM_ERROR @ 12935.245000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
  UVM_INFO @ 12935.245000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aon_timer_wdog_bite_reset has 1 failures.
  - 0.chip_sw_aon_timer_wdog_bite_reset.42855867761745693234601554918087477953608781620421445375956680018478154486663
    Line 400, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
      Offending '(rstreqs[1] && (reset_cause == HwReq))'
  UVM_ERROR @ 7543.565500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
  UVM_INFO @ 7543.565500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.15555139973493138849022040199813662446050579148827222728234795850117552130449
    Line 500, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.63740102303897929024341392239316863825216549794766993629739236613310526857401
    Line 497, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.83644465251941457321023317586887225453155632483126878928968550166489407774635
    Line 503, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.21674949309770174676339487741844120744054195095390844135078340298878174646079
    Line 506, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.49886524758191290374221314939747888545673892219739023583536922439469173442884
    Line 505, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.44846206982018822138531584760445473862371595904388005521521886746837053614180
    Line 479, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.38770413344108455191450365733105616328827289465561371850754993139153006065596
    Line 468, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.38739006857028653995594337993871996499117093099531837549074920176881866185964
    Line 492, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' has 2 failures:
- Test chip_sw_otp_ctrl_escalation has 1 failures.
  - 0.chip_sw_otp_ctrl_escalation.6436307514420685002420634250480035864361011911148857398518491117540226269427
    Line 397, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_escalation/latest/run.log
```
      Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
  UVM_ERROR @ 2939.022334 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
  UVM_INFO @ 2939.022334 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_csrng_fuse_en_sw_app_read_test has 1 failures.
  - 0.chip_sw_csrng_fuse_en_sw_app_read_test.104776358328485344242300577921707360850699288760549692615711225826537128711384
    Line 400, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
      Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
  UVM_ERROR @ 2821.467448 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
  UVM_INFO @ 2821.467448 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 2 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.91755140458684033118468771861949263811034877285800273487350710536478751811340
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.155s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.27408920073543603436415043814207401253926913243150880737219720171185375491851
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 0.165s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.97852428484317593733257175762630559000700003093592385379471978220447320943998
    Line 560, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.39757678187094000937486892085618012074624373728557907147484097825256527631772
    Line 509, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.83012831807928293971564692957957923031065230884727003788554266507404959313401
    Line 595, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.47648577395266349968849861665798432467699882438472293157152409351463360186389
    Line 505, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.17420720865618513819390784370692150005104502785733248062310847190206219201073
    Line 400, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 2431.634696 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 2431.634696 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to * has 1 failures:
- Test chip_sw_otp_ctrl_lc_signals_rma has 1 failures.
  - 0.chip_sw_otp_ctrl_lc_signals_rma.37569354078028447541062545853003586950926081397322428360485626467997072981364
    Line 428, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_rma/latest/run.log
```
  UVM_ERROR @ 7251.072187 us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to 0x0
  UVM_INFO @ 7251.072187 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_rot_auth_config_test_sim_dv(sw/device/tests/otp_ctrl_rot_auth_config_test.c:22)] CHECK-STATUS-fail: @@@:* = ErrorError has 1 failures:
- Test chip_sw_otp_ctrl_rot_auth_config has 1 failures.
  - 0.chip_sw_otp_ctrl_rot_auth_config.9812162834350048276910687852363601306195815058048350191861780157040895093823
    Line 442, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_rot_auth_config/latest/run.log
```
  UVM_ERROR @ 31721.441923 us: (sw_logger_if.sv:526) [otp_ctrl_rot_auth_config_test_sim_dv(sw/device/tests/otp_ctrl_rot_auth_config_test.c:22)] CHECK-STATUS-fail: @@@:0 = ErrorError
  UVM_INFO @ 31721.441923 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@117814) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.36225320469846086086336660515699155551623667898567215287748181033392259646694
Line 419, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 4551.564706 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@117814) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h1  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4551.564706 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 1 failures.
  - 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.28290031306071518563898838125550411685065104373546304237585504440941491172209
    Line 414, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  UVM_ERROR @ 34562.700813 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 34562.700813 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.105735813499476953138599138544718151151888229430462663516212074241172999231525
    Line 390, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 2919.378578 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 42!
  UVM_INFO @ 2919.378578 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.115224642346373302237718415000857376369769156154004457480391578810455588309085
    Line 398, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 2642.517769 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 2642.517769 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job timed out after * minutes has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_pings has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_pings.60088443979224054113773674308154785226332116672354954471783615259429763591611
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest/run.log
```
  Job timed out after 240 minutes
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: *. has 1 failures:
- Test chip_sw_hmac_oneshot has 1 failures.
  - 0.chip_sw_hmac_oneshot.12266353342637720062802558649990244421593432006420810386590671533684760952358
    Line 394, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_oneshot/latest/run.log
```
  UVM_ERROR @ 2764.545640 us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: 8000534a.
  UVM_INFO @ 2764.545640 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(reset_cause == HwReq)' has 1 failures:
- Test chip_sw_sensor_ctrl_alert has 1 failures.
  - 0.chip_sw_sensor_ctrl_alert.8498289041356001386101493137665590174660031022460191731084902079421516250319
    Line 427, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sensor_ctrl_alert/latest/run.log
```
      Offending '(reset_cause == HwReq)'
  UVM_ERROR @ 4537.378654 us: (pwrmgr_rstreqs_sva_if.sv:98) [ASSERT FAILED] SwResetSetCause_A
  UVM_INFO @ 4537.378654 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@34180) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.40421540359456017414241814599614293869441219088535612308789007988849784791978
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2011.361250 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@34180) { a_addr: 'h10758  a_data: 'h7e7bc2f5  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h16  a_opcode: 'h4  a_user: 'h18142  d_param: 'h0  d_source: 'h16  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2011.361250 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. has 1 failures:
- Test chip_sw_rv_core_ibex_lockstep_glitch has 1 failures.
  - 0.chip_sw_rv_core_ibex_lockstep_glitch.114945331551382339851632360717452976232375899515079892575022466063037550031754
    Line 401, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
```
  UVM_FATAL @ 2181.129296 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
  UVM_INFO @ 2181.129296 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.8518328666686488365111363275922432194634969394864810077850266157750702967430
    Line 398, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 3583.396000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3583.396000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.72122698526533837795106966881318328228030561455496427193331022680812274591361
    Line 409, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 3412.388000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3412.388000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.45785826691990345382836186106150097682497320533372145356035001575131288807414
    Line 429, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 15221.706320 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 15221.706320 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.5119713953637344504600335321872668258596582101105280243268491828523139017061
    Line 465, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.20691427837585714077760814390837870542590829963945688900756045773094468127781
    Line 484, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred! has 1 failures:
- Test rom_e2e_jtag_debug_dev has 1 failures.
  - 0.rom_e2e_jtag_debug_dev.22848829984762025023389274585910884123202707616922933403493326812254214933232
    Line 422, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log
```
  UVM_FATAL @ 14818.872385 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 14818.872385 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_sw_lc_raw_unlock_vseq.sv:57) [chip_sw_lc_raw_unlock_vseq] Timed out waiting for clkmgr to confirm extclk enablement has 1 failures:
- Test rom_raw_unlock has 1 failures.
  - 0.rom_raw_unlock.14646918909488299707454671247132641693606887860524326748228440763914969951038
    Line 422, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_raw_unlock/latest/run.log
```
  UVM_FATAL @ 16312.598435 us: (chip_sw_lc_raw_unlock_vseq.sv:57) [uvm_test_top.env.virtual_sequencer.chip_sw_lc_raw_unlock_vseq] Timed out waiting for clkmgr to confirm extclk enablement
  UVM_INFO @ 16312.598435 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@213348) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

0.chip_csr_mem_rw_with_rand_reset.20111488676485515116721565117325854581117415160743676704298187927007606261210
Line 239, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 6249.861818 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@213348) { a_addr: 'h104c8  a_data: 'ha14da4a3  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h15  a_opcode: 'h4  a_user: 'h19979  d_param: 'h0  d_source: 'h15  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 6249.861818 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---