| V1 |
smoke |
adc_ctrl_smoke |
13.340s |
|
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
adc_ctrl_csr_hw_reset |
1.860s |
|
1 |
1 |
100.00 |
| V1 |
csr_rw |
adc_ctrl_csr_rw |
1.070s |
|
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
adc_ctrl_csr_bit_bash |
30.720s |
|
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
adc_ctrl_csr_aliasing |
4.040s |
|
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
adc_ctrl_csr_mem_rw_with_rand_reset |
1.200s |
|
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
adc_ctrl_csr_rw |
1.070s |
|
1 |
1 |
100.00 |
|
|
adc_ctrl_csr_aliasing |
4.040s |
|
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
6 |
6 |
100.00 |
| V2 |
filters_polled |
adc_ctrl_filters_polled |
4.652m |
|
1 |
1 |
100.00 |
| V2 |
filters_polled_fixed |
adc_ctrl_filters_polled_fixed |
13.665m |
|
1 |
1 |
100.00 |
| V2 |
filters_interrupt |
adc_ctrl_filters_interrupt |
1.767m |
|
1 |
1 |
100.00 |
| V2 |
filters_interrupt_fixed |
adc_ctrl_filters_interrupt_fixed |
2.428m |
|
1 |
1 |
100.00 |
| V2 |
filters_wakeup |
adc_ctrl_filters_wakeup |
6.218m |
|
1 |
1 |
100.00 |
| V2 |
filters_wakeup_fixed |
adc_ctrl_filters_wakeup_fixed |
11.417m |
|
1 |
1 |
100.00 |
| V2 |
filters_both |
adc_ctrl_filters_both |
3.846m |
|
1 |
1 |
100.00 |
| V2 |
clock_gating |
adc_ctrl_clock_gating |
3.709m |
|
1 |
1 |
100.00 |
| V2 |
poweron_counter |
adc_ctrl_poweron_counter |
5.090s |
|
1 |
1 |
100.00 |
| V2 |
lowpower_counter |
adc_ctrl_lowpower_counter |
12.420s |
|
1 |
1 |
100.00 |
| V2 |
fsm_reset |
adc_ctrl_fsm_reset |
17.370s |
|
1 |
1 |
100.00 |
| V2 |
stress_all |
adc_ctrl_stress_all |
1.689m |
|
1 |
1 |
100.00 |
| V2 |
alert_test |
adc_ctrl_alert_test |
1.400s |
|
1 |
1 |
100.00 |
| V2 |
intr_test |
adc_ctrl_intr_test |
0.880s |
|
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
adc_ctrl_tl_errors |
2.260s |
|
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
adc_ctrl_tl_errors |
2.260s |
|
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
adc_ctrl_csr_hw_reset |
1.860s |
|
1 |
1 |
100.00 |
|
|
adc_ctrl_csr_rw |
1.070s |
|
1 |
1 |
100.00 |
|
|
adc_ctrl_csr_aliasing |
4.040s |
|
1 |
1 |
100.00 |
|
|
adc_ctrl_same_csr_outstanding |
3.660s |
|
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
adc_ctrl_csr_hw_reset |
1.860s |
|
1 |
1 |
100.00 |
|
|
adc_ctrl_csr_rw |
1.070s |
|
1 |
1 |
100.00 |
|
|
adc_ctrl_csr_aliasing |
4.040s |
|
1 |
1 |
100.00 |
|
|
adc_ctrl_same_csr_outstanding |
3.660s |
|
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
16 |
16 |
100.00 |
| V2S |
tl_intg_err |
adc_ctrl_sec_cm |
9.920s |
|
1 |
1 |
100.00 |
|
|
adc_ctrl_tl_intg_err |
12.690s |
|
1 |
1 |
100.00 |
| V2S |
sec_cm_bus_integrity |
adc_ctrl_tl_intg_err |
12.690s |
|
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
2 |
2 |
100.00 |
| V3 |
stress_all_with_rand_reset |
adc_ctrl_stress_all_with_rand_reset |
13.110s |
|
1 |
1 |
100.00 |
| V3 |
|
TOTAL |
|
|
1 |
1 |
100.00 |
|
|
TOTAL |
|
|
25 |
25 |
100.00 |