I2C Simulation Results

Thursday November 06 2025 19:19:18 UTC

GitHub Revision: 8507ebb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	38.230s		1	1	100.00
V1	target_smoke	i2c_target_smoke	23.260s		1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.710s		1	1	100.00
V1	csr_rw	i2c_csr_rw	0.640s		1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	2.130s		1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.510s		1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	0.740s		1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.640s		1	1	100.00
		i2c_csr_aliasing	1.510s		1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	3.020s		0	1	0.00
V2	host_stress_all	i2c_host_stress_all	4.262m		0	1	0.00
V2	host_maxperf	i2c_host_perf	13.315m		1	1	100.00
V2	host_override	i2c_host_override	0.620s		1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	36.470s		1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	43.370s		1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	0.990s		1	1	100.00
		i2c_host_fifo_fmt_empty	13.160s		1	1	100.00
		i2c_host_fifo_reset_rx	2.420s		1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	42.760s		1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	26.690s		1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.640s		1	1	100.00
V2	target_glitch	i2c_target_glitch	1.980s		0	1	0.00
V2	target_stress_all	i2c_target_stress_all	40.310s		1	1	100.00
V2	target_maxperf	i2c_target_perf	3.090s		1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	5.060s		1	1	100.00
		i2c_target_intr_smoke	3.430s		1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	0.810s		1	1	100.00
		i2c_target_fifo_reset_tx	0.890s		1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	14.616m		1	1	100.00
		i2c_target_stress_rd	5.060s		1	1	100.00
		i2c_target_intr_stress_wr	38.740s		1	1	100.00
V2	target_timeout	i2c_target_timeout	4.060s		1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	12.470s		1	1	100.00
V2	bad_address	i2c_target_bad_addr	4.730s		1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	5.930s		0	1	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	1.840s		1	1	100.00
		i2c_target_fifo_watermarks_tx	0.920s		1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	13.315m		1	1	100.00
		i2c_host_perf_precise	1.330s		1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	26.690s		1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	2.280s		1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	1.940s		1	1	100.00
		i2c_target_nack_acqfull_addr	1.740s		1	1	100.00
		i2c_target_nack_txstretch	1.320s		1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	13.000s		1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	1.510s		1	1	100.00
V2	alert_test	i2c_alert_test	0.620s		1	1	100.00
V2	intr_test	i2c_intr_test	0.700s		1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	0.990s		1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	0.990s		1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.710s		1	1	100.00
		i2c_csr_rw	0.640s		1	1	100.00
		i2c_csr_aliasing	1.510s		1	1	100.00
		i2c_same_csr_outstanding	1.090s		1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.710s		1	1	100.00
		i2c_csr_rw	0.640s		1	1	100.00
		i2c_csr_aliasing	1.510s		1	1	100.00
		i2c_same_csr_outstanding	1.090s		1	1	100.00
V2		TOTAL			34	38	89.47
V2S	tl_intg_err	i2c_tl_intg_err	1.640s		1	1	100.00
		i2c_sec_cm	0.940s		1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	1.640s		1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	5.370s		0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	0.720s		0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	23.650s		0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			43	50	86.00

Failure Buckets

• UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 2 failures:

  • Test i2c_host_error_intr has 1 failures.

    • 0.i2c_host_error_intr.6388807319823261622285632049312515708236549539768521781583920316482538592664
      Line 99, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

        UVM_ERROR @ 236273763 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @ 236273763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_host_stress_all has 1 failures.

    • 0.i2c_host_stress_all.97905712835997598993567788181827253666671252811172578558123013919002181922952
      Line 128, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

        UVM_ERROR @ 11312585919 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @ 11312585919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.113773435270842064422097260857867572265599693365059837361026286158522268035513
      Line 90, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1374507480 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1374507480 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.107433308790510079649743917334323668618081740422319253079600875224018839660924
      Line 127, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3763150874 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 3763150874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_target_glitch has 1 failures.

    • 0.i2c_target_glitch.11630238870761248636369956249188739206864202906890805623183238426079241145480
      Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

        UVM_ERROR @ 565818972 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
        UVM_INFO @ 565818972 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.71250041941655981351508213939083530999473792583575892123814779195942792422820
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @  64877227 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 30 [0x1e])
        UVM_INFO @  64877227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:

  • Test i2c_target_hrst has 1 failures.

    • 0.i2c_target_hrst.49263744652682351003552242356681824054581543960357786253654348333562441308744
      Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log

        UVM_FATAL @ 11141465288 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
        UVM_INFO @ 11141465288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---