KMAC/UNMASKED Simulation Results

Thursday November 06 2025 19:19:18 UTC

GitHub Revision: 8507ebb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke kmac_smoke 25.150s 1 1 100.00
V1 csr_hw_reset kmac_csr_hw_reset 1.100s 1 1 100.00
V1 csr_rw kmac_csr_rw 1.010s 1 1 100.00
V1 csr_bit_bash kmac_csr_bit_bash 6.910s 1 1 100.00
V1 csr_aliasing kmac_csr_aliasing 2.930s 1 1 100.00
V1 csr_mem_rw_with_rand_reset kmac_csr_mem_rw_with_rand_reset 1.330s 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr kmac_csr_rw 1.010s 1 1 100.00
kmac_csr_aliasing 2.930s 1 1 100.00
V1 mem_walk kmac_mem_walk 1.030s 1 1 100.00
V1 mem_partial_access kmac_mem_partial_access 1.150s 1 1 100.00
V1 TOTAL 8 8 100.00
V2 long_msg_and_output kmac_long_msg_and_output 7.016m 1 1 100.00
V2 burst_write kmac_burst_write 2.256m 1 1 100.00
V2 test_vectors kmac_test_vectors_sha3_224 19.342m 1 1 100.00
kmac_test_vectors_sha3_256 23.586m 1 1 100.00
kmac_test_vectors_sha3_384 13.231m 1 1 100.00
kmac_test_vectors_sha3_512 9.883m 1 1 100.00
kmac_test_vectors_shake_128 2.729m 1 1 100.00
kmac_test_vectors_shake_256 4.202m 1 1 100.00
kmac_test_vectors_kmac 2.010s 1 1 100.00
kmac_test_vectors_kmac_xof 1.700s 1 1 100.00
V2 sideload kmac_sideload 1.756m 1 1 100.00
V2 app kmac_app 2.585m 1 1 100.00
V2 app_with_partial_data kmac_app_with_partial_data 2.101m 1 1 100.00
V2 entropy_refresh kmac_entropy_refresh 1.436m 1 1 100.00
V2 error kmac_error 46.990s 1 1 100.00
V2 key_error kmac_key_error 1.190s 1 1 100.00
V2 sideload_invalid kmac_sideload_invalid 1.870s 1 1 100.00
V2 edn_timeout_error kmac_edn_timeout_error 12.720s 1 1 100.00
V2 entropy_mode_error kmac_entropy_mode_error 15.550s 1 1 100.00
V2 entropy_ready_error kmac_entropy_ready_error 49.570s 1 1 100.00
V2 lc_escalation kmac_lc_escalation 1.710s 1 1 100.00
V2 stress_all kmac_stress_all 7.774m 1 1 100.00
V2 intr_test kmac_intr_test 0.760s 1 1 100.00
V2 alert_test kmac_alert_test 1.120s 1 1 100.00
V2 tl_d_oob_addr_access kmac_tl_errors 1.770s 1 1 100.00
V2 tl_d_illegal_access kmac_tl_errors 1.770s 1 1 100.00
V2 tl_d_outstanding_access kmac_csr_hw_reset 1.100s 1 1 100.00
kmac_csr_rw 1.010s 1 1 100.00
kmac_csr_aliasing 2.930s 1 1 100.00
kmac_same_csr_outstanding 1.850s 1 1 100.00
V2 tl_d_partial_access kmac_csr_hw_reset 1.100s 1 1 100.00
kmac_csr_rw 1.010s 1 1 100.00
kmac_csr_aliasing 2.930s 1 1 100.00
kmac_same_csr_outstanding 1.850s 1 1 100.00
V2 TOTAL 26 26 100.00
V2S shadow_reg_update_error kmac_shadow_reg_errors 1.870s 1 1 100.00
V2S shadow_reg_read_clear_staged_value kmac_shadow_reg_errors 1.870s 1 1 100.00
V2S shadow_reg_storage_error kmac_shadow_reg_errors 1.870s 1 1 100.00
V2S shadowed_reset_glitch kmac_shadow_reg_errors 1.870s 1 1 100.00
V2S shadow_reg_update_error_with_csr_rw kmac_shadow_reg_errors_with_csr_rw 2.900s 1 1 100.00
V2S tl_intg_err kmac_sec_cm 29.470s 1 1 100.00
kmac_tl_intg_err 3.340s 1 1 100.00
V2S sec_cm_bus_integrity kmac_tl_intg_err 3.340s 1 1 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi kmac_lc_escalation 1.710s 1 1 100.00
V2S sec_cm_sw_key_key_masking kmac_smoke 25.150s 1 1 100.00
V2S sec_cm_key_sideload kmac_sideload 1.756m 1 1 100.00
V2S sec_cm_cfg_shadowed_config_shadow kmac_shadow_reg_errors 1.870s 1 1 100.00
V2S sec_cm_fsm_sparse kmac_sec_cm 29.470s 1 1 100.00
V2S sec_cm_ctr_redun kmac_sec_cm 29.470s 1 1 100.00
V2S sec_cm_packer_ctr_redun kmac_sec_cm 29.470s 1 1 100.00
V2S sec_cm_cfg_shadowed_config_regwen kmac_smoke 25.150s 1 1 100.00
V2S sec_cm_fsm_global_esc kmac_lc_escalation 1.710s 1 1 100.00
V2S sec_cm_fsm_local_esc kmac_sec_cm 29.470s 1 1 100.00
V2S sec_cm_absorbed_ctrl_mubi kmac_mubi 1.018m 1 1 100.00
V2S sec_cm_sw_cmd_ctrl_sparse kmac_smoke 25.150s 1 1 100.00
V2S TOTAL 5 5 100.00
V3 stress_all_with_rand_reset kmac_stress_all_with_rand_reset 2.352m 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 40 40 100.00