OTBN Simulation Results

Thursday November 06 2025 19:19:18 UTC

GitHub Revision: 8507ebb

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke otbn_smoke 6.000s 189.182us 0 1 0.00
V1 single_binary otbn_single 11.000s 97.505us 0 1 0.00
V1 csr_hw_reset otbn_csr_hw_reset 3.000s 47.561us 1 1 100.00
V1 csr_rw otbn_csr_rw 3.000s 13.013us 1 1 100.00
V1 csr_bit_bash otbn_csr_bit_bash 5.000s 38.918us 1 1 100.00
V1 csr_aliasing otbn_csr_aliasing 4.000s 15.941us 1 1 100.00
V1 csr_mem_rw_with_rand_reset otbn_csr_mem_rw_with_rand_reset 7.000s 42.052us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr otbn_csr_rw 3.000s 13.013us 1 1 100.00
otbn_csr_aliasing 4.000s 15.941us 1 1 100.00
V1 mem_walk otbn_mem_walk 29.000s 353.525us 1 1 100.00
V1 mem_partial_access otbn_mem_partial_access 17.000s 365.266us 1 1 100.00
V1 TOTAL 7 9 77.78
V2 reset_recovery otbn_reset 32.000s 138.697us 0 1 0.00
V2 multi_error otbn_multi_err 54.000s 290.200us 0 1 0.00
V2 back_to_back otbn_multi 30.000s 144.128us 0 1 0.00
V2 stress_all otbn_stress_all 19.000s 56.701us 0 1 0.00
V2 lc_escalation otbn_escalate 4.000s 24.047us 1 1 100.00
V2 zero_state_err_urnd otbn_zero_state_err_urnd 5.000s 87.560us 1 1 100.00
V2 sw_errs_fatal_chk otbn_sw_errs_fatal_chk 6.000s 37.676us 0 1 0.00
V2 alert_test otbn_alert_test 3.000s 17.861us 1 1 100.00
V2 intr_test otbn_intr_test 4.000s 14.852us 1 1 100.00
V2 tl_d_oob_addr_access otbn_tl_errors 5.000s 87.369us 1 1 100.00
V2 tl_d_illegal_access otbn_tl_errors 5.000s 87.369us 1 1 100.00
V2 tl_d_outstanding_access otbn_csr_hw_reset 3.000s 47.561us 1 1 100.00
otbn_csr_rw 3.000s 13.013us 1 1 100.00
otbn_csr_aliasing 4.000s 15.941us 1 1 100.00
otbn_same_csr_outstanding 4.000s 27.602us 1 1 100.00
V2 tl_d_partial_access otbn_csr_hw_reset 3.000s 47.561us 1 1 100.00
otbn_csr_rw 3.000s 13.013us 1 1 100.00
otbn_csr_aliasing 4.000s 15.941us 1 1 100.00
otbn_same_csr_outstanding 4.000s 27.602us 1 1 100.00
V2 TOTAL 6 11 54.55
V2S mem_integrity otbn_imem_err 8.000s 63.196us 0 1 0.00
otbn_dmem_err 6.000s 19.713us 0 1 0.00
V2S internal_integrity otbn_alu_bignum_mod_err 8.000s 66.932us 0 1 0.00
otbn_controller_ispr_rdata_err 6.000s 218.074us 0 1 0.00
otbn_mac_bignum_acc_err 10.000s 113.396us 0 1 0.00
otbn_urnd_err 6.000s 80.723us 0 1 0.00
V2S illegal_bus_access otbn_illegal_mem_acc 4.000s 24.153us 1 1 100.00
V2S otbn_mem_gnt_acc_err otbn_mem_gnt_acc_err 24.000s 10.006ms 0 1 0.00
V2S otbn_non_sec_partial_wipe otbn_partial_wipe 5.000s 41.233us 1 1 100.00
V2S tl_intg_err otbn_sec_cm 4.000s 4.097us 0 1 0.00
otbn_tl_intg_err 13.000s 565.190us 1 1 100.00
V2S passthru_mem_tl_intg_err otbn_passthru_mem_tl_intg_err 18.000s 120.086us 1 1 100.00
V2S prim_fsm_check otbn_sec_cm 4.000s 4.097us 0 1 0.00
V2S prim_count_check otbn_sec_cm 4.000s 4.097us 0 1 0.00
V2S sec_cm_mem_scramble otbn_smoke 6.000s 189.182us 0 1 0.00
V2S sec_cm_data_mem_integrity otbn_dmem_err 6.000s 19.713us 0 1 0.00
V2S sec_cm_instruction_mem_integrity otbn_imem_err 8.000s 63.196us 0 1 0.00
V2S sec_cm_bus_integrity otbn_tl_intg_err 13.000s 565.190us 1 1 100.00
V2S sec_cm_controller_fsm_global_esc otbn_escalate 4.000s 24.047us 1 1 100.00
V2S sec_cm_controller_fsm_local_esc otbn_imem_err 8.000s 63.196us 0 1 0.00
otbn_dmem_err 6.000s 19.713us 0 1 0.00
otbn_zero_state_err_urnd 5.000s 87.560us 1 1 100.00
otbn_illegal_mem_acc 4.000s 24.153us 1 1 100.00
otbn_sec_cm 4.000s 4.097us 0 1 0.00
V2S sec_cm_controller_fsm_sparse otbn_sec_cm 4.000s 4.097us 0 1 0.00
V2S sec_cm_scramble_key_sideload otbn_single 11.000s 97.505us 0 1 0.00
V2S sec_cm_scramble_ctrl_fsm_local_esc otbn_imem_err 8.000s 63.196us 0 1 0.00
otbn_dmem_err 6.000s 19.713us 0 1 0.00
otbn_zero_state_err_urnd 5.000s 87.560us 1 1 100.00
otbn_illegal_mem_acc 4.000s 24.153us 1 1 100.00
otbn_sec_cm 4.000s 4.097us 0 1 0.00
V2S sec_cm_scramble_ctrl_fsm_sparse otbn_sec_cm 4.000s 4.097us 0 1 0.00
V2S sec_cm_start_stop_ctrl_fsm_global_esc otbn_escalate 4.000s 24.047us 1 1 100.00
V2S sec_cm_start_stop_ctrl_fsm_local_esc otbn_imem_err 8.000s 63.196us 0 1 0.00
otbn_dmem_err 6.000s 19.713us 0 1 0.00
otbn_zero_state_err_urnd 5.000s 87.560us 1 1 100.00
otbn_illegal_mem_acc 4.000s 24.153us 1 1 100.00
otbn_sec_cm 4.000s 4.097us 0 1 0.00
V2S sec_cm_start_stop_ctrl_fsm_sparse otbn_sec_cm 4.000s 4.097us 0 1 0.00
V2S sec_cm_data_reg_sw_sca otbn_single 11.000s 97.505us 0 1 0.00
V2S sec_cm_ctrl_redun otbn_ctrl_redun 5.000s 35.968us 0 1 0.00
V2S sec_cm_pc_ctrl_flow_redun otbn_pc_ctrl_flow_redun 8.000s 28.801us 0 1 0.00
V2S sec_cm_rnd_bus_consistency otbn_rnd_sec_cm 40.000s 163.972us 0 1 0.00
V2S sec_cm_rnd_rng_digest otbn_rnd_sec_cm 40.000s 163.972us 0 1 0.00
V2S sec_cm_rf_base_data_reg_sw_integrity otbn_rf_base_intg_err 5.000s 64.482us 0 1 0.00
V2S sec_cm_rf_base_data_reg_sw_glitch_detect otbn_sec_cm 4.000s 4.097us 0 1 0.00
V2S sec_cm_stack_wr_ptr_ctr_redun otbn_sec_cm 4.000s 4.097us 0 1 0.00
V2S sec_cm_rf_bignum_data_reg_sw_integrity otbn_rf_bignum_intg_err 8.000s 220.922us 0 1 0.00
V2S sec_cm_rf_bignum_data_reg_sw_glitch_detect otbn_sec_cm 4.000s 4.097us 0 1 0.00
V2S sec_cm_loop_stack_ctr_redun otbn_sec_cm 4.000s 4.097us 0 1 0.00
V2S sec_cm_loop_stack_addr_integrity otbn_stack_addr_integ_chk 12.000s 214.449us 0 1 0.00
V2S sec_cm_call_stack_addr_integrity otbn_stack_addr_integ_chk 12.000s 214.449us 0 1 0.00
V2S sec_cm_start_stop_ctrl_state_consistency otbn_sec_wipe_err 5.000s 5.431us 0 1 0.00
V2S sec_cm_data_mem_sec_wipe otbn_single 11.000s 97.505us 0 1 0.00
V2S sec_cm_instruction_mem_sec_wipe otbn_single 11.000s 97.505us 0 1 0.00
V2S sec_cm_data_reg_sw_sec_wipe otbn_single 11.000s 97.505us 0 1 0.00
V2S sec_cm_write_mem_integrity otbn_multi 30.000s 144.128us 0 1 0.00
V2S sec_cm_ctrl_flow_count otbn_single 11.000s 97.505us 0 1 0.00
V2S sec_cm_ctrl_flow_sca otbn_single 11.000s 97.505us 0 1 0.00
V2S sec_cm_data_mem_sw_noaccess otbn_sw_no_acc 20.000s 89.570us 0 1 0.00
V2S sec_cm_key_sideload otbn_single 11.000s 97.505us 0 1 0.00
V2S sec_cm_tlul_fifo_ctr_redun otbn_sec_cm 4.000s 4.097us 0 1 0.00
V2S TOTAL 4 20 20.00
V3 stress_all_with_rand_reset otbn_stress_all_with_rand_reset 1.800m 1.233ms 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 17 41 41.46

Failure Buckets