PATTGEN Simulation Results

Thursday November 06 2025 19:19:18 UTC

GitHub Revision: `8507ebb`

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	2.000s	199.384us	1	1	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	1.000s	34.220us	1	1	100.00
V1	csr_rw	pattgen_csr_rw	1.000s	37.769us	1	1	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	3.000s	991.305us	1	1	100.00
V1	csr_aliasing	pattgen_csr_aliasing	1.000s	36.651us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	2.000s	37.371us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	1.000s	37.769us	1	1	100.00
		pattgen_csr_aliasing	1.000s	36.651us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	perf	pattgen_perf	17.000s	2.637ms	1	1	100.00
V2	cnt_rollover	cnt_rollover	30.000s	4.516ms	1	1	100.00
V2	error	pattgen_error	2.000s	78.063us	1	1	100.00
V2	stress_all	pattgen_stress_all	2.000s	331.433us	0	1	0.00
V2	alert_test	pattgen_alert_test	1.000s	42.905us	1	1	100.00
V2	intr_test	pattgen_intr_test	1.000s	14.171us	1	1	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	3.000s	102.860us	1	1	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	3.000s	102.860us	1	1	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	1.000s	34.220us	1	1	100.00
		pattgen_csr_rw	1.000s	37.769us	1	1	100.00
		pattgen_csr_aliasing	1.000s	36.651us	1	1	100.00
		pattgen_same_csr_outstanding	1.000s	25.309us	1	1	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	1.000s	34.220us	1	1	100.00
		pattgen_csr_rw	1.000s	37.769us	1	1	100.00
		pattgen_csr_aliasing	1.000s	36.651us	1	1	100.00
		pattgen_same_csr_outstanding	1.000s	25.309us	1	1	100.00
V2		TOTAL			7	8	87.50
V2S	tl_intg_err	pattgen_tl_intg_err	2.000s	322.302us	1	1	100.00
		pattgen_sec_cm	1.000s	65.348us	1	1	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	2.000s	322.302us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	40.000s	20.771ms	0	1	0.00
V3		TOTAL			0	1	0.00
	Unmapped tests	pattgen_inactive_level	51.000s	10.039ms	0	1	0.00
		TOTAL			15	18	83.33

Failure Buckets

UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=20) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 0.pattgen_inactive_level.61686916519615421348930647328051243422480913673847585432186839664100677551119
    Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10038600301 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x27e88650, Comparison=CompareOpEq, exp_data=0x0, call_count=20)
  UVM_INFO @ 10038600301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_vseq.sv:1230) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

Test pattgen_stress_all_with_rand_reset has 1 failures.

0.pattgen_stress_all_with_rand_reset.80502956684271111973057198910573345717074709304155025397973813426699422083423
Line 113, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2513380056 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 2513419581 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 2513419581 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 1/10
  UVM_INFO @ 2513506537 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared: has 1 failures:
- Test pattgen_stress_all has 1 failures.
  - 0.pattgen_stress_all.112746074300804687153080009829067198851302965149540269310243655183567902496746
    Line 156, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all/latest/run.log
```
  UVM_ERROR @ 331433168 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
  ------------------------------------
  Name      Type          Size  Value
  ------------------------------------
  exp_item  pattgen_item  -     @10253
```