RV_DM/USE_JTAG_INTERFACE Simulation Results

Thursday November 06 2025 19:19:18 UTC

GitHub Revision: `8507ebb`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Passing	Total	Pass Rate
V1	smoke	rv_dm_smoke	6.880s	1	1	100.00
V1	jtag_dtm_csr_hw_reset	rv_dm_jtag_dtm_csr_hw_reset	1.250s	1	1	100.00
V1	jtag_dtm_csr_rw	rv_dm_jtag_dtm_csr_rw	1.330s	1	1	100.00
V1	jtag_dtm_csr_bit_bash	rv_dm_jtag_dtm_csr_bit_bash	29.300s	1	1	100.00
V1	jtag_dtm_csr_aliasing	rv_dm_jtag_dtm_csr_aliasing	1.670s	1	1	100.00
V1	jtag_dmi_csr_hw_reset	rv_dm_jtag_dmi_csr_hw_reset	38.070s	1	1	100.00
V1	jtag_dmi_csr_rw	rv_dm_jtag_dmi_csr_rw	5.220s	1	1	100.00
V1	jtag_dmi_csr_bit_bash	rv_dm_jtag_dmi_csr_bit_bash	1.929m	1	1	100.00
V1	jtag_dmi_csr_aliasing	rv_dm_jtag_dmi_csr_aliasing	1.480m	1	1	100.00
V1	jtag_dmi_cmderr_busy	rv_dm_cmderr_busy	1.470s	1	1	100.00
V1	jtag_dmi_cmderr_not_supported	rv_dm_cmderr_not_supported	0.910s	1	1	100.00
V1	cmderr_exception	rv_dm_cmderr_exception	2.100s	1	1	100.00
V1	mem_tl_access_resuming	rv_dm_mem_tl_access_resuming	1.860s	1	1	100.00
V1	mem_tl_access_halted	rv_dm_mem_tl_access_halted	0.940s	1	1	100.00
V1	cmderr_halt_resume	rv_dm_cmderr_halt_resume	2.590s	1	1	100.00
V1	dataaddr_rw_access	rv_dm_dataaddr_rw_access	0.920s	1	1	100.00
V1	halt_resume	rv_dm_halt_resume_whereto	1.150s	1	1	100.00
V1	progbuf_busy	rv_dm_cmderr_busy	1.470s	1	1	100.00
V1	abstractcmd_status	rv_dm_abstractcmd_status	1.150s	1	1	100.00
V1	progbuf_read_write_execute	rv_dm_progbuf_read_write_execute	1.770s	1	1	100.00
V1	progbuf_exception	rv_dm_cmderr_exception	2.100s	1	1	100.00
V1	rom_read_access	rv_dm_rom_read_access	0.850s	1	1	100.00
V1	csr_hw_reset	rv_dm_csr_hw_reset	1.490s	1	1	100.00
V1	csr_rw	rv_dm_csr_rw	1.420s	1	1	100.00
V1	csr_bit_bash	rv_dm_csr_bit_bash	52.700s	1	1	100.00
V1	csr_aliasing	rv_dm_csr_aliasing	55.220s	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_dm_csr_mem_rw_with_rand_reset	1.880s	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_dm_csr_aliasing	55.220s	1	1	100.00
		rv_dm_csr_rw	1.420s	1	1	100.00
V1	mem_walk	rv_dm_mem_walk	1.240s	1	1	100.00
V1	mem_partial_access	rv_dm_mem_partial_access	1.070s	1	1	100.00
V1		TOTAL		27	27	100.00
V2	idcode	rv_dm_smoke	6.880s	1	1	100.00
V2	jtag_dtm_hard_reset	rv_dm_jtag_dtm_hard_reset	0.920s	1	1	100.00
V2	jtag_dtm_idle_hint	rv_dm_jtag_dtm_idle_hint	1.570s	1	1	100.00
V2	jtag_dmi_failed_op	rv_dm_dmi_failed_op	1.590s	1	1	100.00
V2	jtag_dmi_dm_inactive	rv_dm_jtag_dmi_dm_inactive	5.890s	1	1	100.00
V2	sba	rv_dm_sba_tl_access	2.606m	0	1	0.00
		rv_dm_delayed_resp_sba_tl_access	2.454m	0	1	0.00
V2	bad_sba	rv_dm_bad_sba_tl_access	1.081m	0	1	0.00
V2	sba_autoincrement	rv_dm_autoincr_sba_tl_access	5.031m	0	1	0.00
V2	jtag_dmi_debug_disabled	rv_dm_jtag_dmi_debug_disabled	1.210s	1	1	100.00
V2	sba_debug_disabled	rv_dm_sba_debug_disabled	2.110s	1	1	100.00
V2	ndmreset_req	rv_dm_ndmreset_req	0.840s	1	1	100.00
V2	hart_unavail	rv_dm_hart_unavail	1.090s	1	1	100.00
V2	tap_ctrl_transitions	rv_dm_tap_fsm	8.810s	1	1	100.00
		rv_dm_tap_fsm_rand_reset	0.900s	0	1	0.00
V2	hartsel_warl	rv_dm_hartsel_warl	0.780s	1	1	100.00
V2	stress_all	rv_dm_stress_all	2.040s	1	1	100.00
V2	alert_test	rv_dm_alert_test	0.980s	1	1	100.00
V2	tl_d_oob_addr_access	rv_dm_tl_errors	0.850s	0	1	0.00
V2	tl_d_illegal_access	rv_dm_tl_errors	0.850s	0	1	0.00
V2	tl_d_outstanding_access	rv_dm_csr_aliasing	55.220s	1	1	100.00
		rv_dm_csr_hw_reset	1.490s	1	1	100.00
		rv_dm_csr_rw	1.420s	1	1	100.00
		rv_dm_same_csr_outstanding	4.980s	1	1	100.00
V2	tl_d_partial_access	rv_dm_csr_aliasing	55.220s	1	1	100.00
		rv_dm_csr_hw_reset	1.490s	1	1	100.00
		rv_dm_csr_rw	1.420s	1	1	100.00
		rv_dm_same_csr_outstanding	4.980s	1	1	100.00
V2		TOTAL		13	19	68.42
V2S	tl_intg_err	rv_dm_sec_cm	1.410s	1	1	100.00
		rv_dm_tl_intg_err	14.310s	1	1	100.00
V2S	sec_cm_bus_integrity	rv_dm_tl_intg_err	14.310s	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	rv_dm_sba_debug_disabled	2.110s	1	1	100.00
		rv_dm_debug_disabled	1.260s	1	1	100.00
V2S	sec_cm_lc_dft_en_intersig_mubi	rv_dm_sba_debug_disabled	2.110s	1	1	100.00
		rv_dm_debug_disabled	1.260s	1	1	100.00
V2S	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi	rv_dm_smoke	6.880s	1	1	100.00
V2S	sec_cm_dm_en_ctrl_lc_gated	rv_dm_buffered_enable	1.560s	1	1	100.00
V2S	sec_cm_sba_tl_lc_gate_fsm_sparse	rv_dm_sparse_lc_gate_fsm	1.420s	1	1	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	rv_dm_sparse_lc_gate_fsm	1.420s	1	1	100.00
V2S	sec_cm_exec_ctrl_mubi	rv_dm_buffered_enable	1.560s	1	1	100.00
V2S		TOTAL		5	5	100.00
V3	stress_all_with_rand_reset	rv_dm_stress_all_with_rand_reset	0.810s	0	1	0.00
V3		TOTAL		0	1	0.00
	Unmapped tests	rv_dm_scanmode	0.780s	1	1	100.00
		TOTAL		46	53	86.79

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:
- Test rv_dm_sba_tl_access has 1 failures.
  - 0.rv_dm_sba_tl_access.64873098894756260298458484007661882486269644080009943379439359738301816679772
    Line 83, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_sba_tl_access/latest/run.log
```
  UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rv_dm_delayed_resp_sba_tl_access has 1 failures.
  - 0.rv_dm_delayed_resp_sba_tl_access.35716127733758781364117696990892649404532274936652044535208314599342592013714
    Line 83, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_delayed_resp_sba_tl_access/latest/run.log
```
  UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rv_dm_bad_sba_tl_access has 1 failures.
  - 0.rv_dm_bad_sba_tl_access.46507797646388488483121434732977543223869706691983940639346773369435839682875
    Line 83, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_bad_sba_tl_access/latest/run.log
```
  UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rv_dm_autoincr_sba_tl_access has 1 failures.
  - 0.rv_dm_autoincr_sba_tl_access.94011136905620354581613652256591851557045525128269843307734010163337513986995
    Line 83, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_autoincr_sba_tl_access/latest/run.log
```
  UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@6514) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test rv_dm_tap_fsm_rand_reset has 1 failures.

0.rv_dm_tap_fsm_rand_reset.77829119228004472195181762677871056525600224175549555554678677987189568734748
Line 76, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_tap_fsm_rand_reset/latest/run.log

  UVM_ERROR @  32650599 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@6514) { a_addr: 'h420a4464  a_data: 'h94047380  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h88  a_opcode: 'h4  a_user: 'h1898d  d_param: 'h0  d_source: 'h88  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @  32650599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@5934) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test rv_dm_stress_all_with_rand_reset has 1 failures.

0.rv_dm_stress_all_with_rand_reset.71841202670234811783111925233494864838518658862431609240417579969290818617297
Line 76, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  25654272 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@5934) { a_addr: 'h8c121678  a_data: 'h3ba6e54d  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h6a  a_opcode: 'h4  a_user: 'h1ba32  d_param: 'h0  d_source: 'h6a  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @  25654272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@5552) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test rv_dm_tl_errors has 1 failures.

0.rv_dm_tl_errors.26447748977247533340555426970712662878758233234387701904884636193905041486839
Line 75, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_tl_errors/latest/run.log

  UVM_ERROR @  42667896 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@5552) { a_addr: 'hccc1a51c  a_data: 'h8ce677e4  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hd7  a_opcode: 'h4  a_user: 'h18a75  d_param: 'h0  d_source: 'hd7  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @  42667896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---