SPI_DEVICE/1R1W Simulation Results

Thursday November 06 2025 19:19:18 UTC

GitHub Revision: 8507ebb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	1.053m		1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.110s		1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.930s		1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	8.570s		1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	5.600s		1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.090s		1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.930s		1	1	100.00
		spi_device_csr_aliasing	5.600s		1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.720s		1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.610s		1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	0.810s		1	1	100.00
V2	mem_parity	spi_device_mem_parity	0.670s		0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	0.690s		0	1	0.00
V2	tpm_read	spi_device_tpm_rw	2.050s		1	1	100.00
V2	tpm_write	spi_device_tpm_rw	2.050s		1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	1.730s		1	1	100.00
		spi_device_tpm_sts_read	0.850s		1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	21.770s		1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	6.470s		1	1	100.00
		spi_device_flash_all	0.750s		1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	10.270s		1	1	100.00
		spi_device_flash_all	0.750s		1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	10.270s		1	1	100.00
		spi_device_flash_all	0.750s		1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	0.750s		1	1	100.00
V2	cmd_read_status	spi_device_intercept	1.610s		1	1	100.00
		spi_device_flash_all	0.750s		1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	1.610s		1	1	100.00
		spi_device_flash_all	0.750s		1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	1.610s		1	1	100.00
		spi_device_flash_all	0.750s		1	1	100.00
V2	cmd_fast_read	spi_device_intercept	1.610s		1	1	100.00
		spi_device_flash_all	0.750s		1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	1.610s		1	1	100.00
		spi_device_flash_all	0.750s		1	1	100.00
V2	flash_cmd_upload	spi_device_upload	22.680s		1	1	100.00
V2	mailbox_command	spi_device_mailbox	10.910s		1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	10.910s		1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	10.910s		1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	31.970s		1	1	100.00
		spi_device_read_buffer_direct	9.170s		1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	10.910s		1	1	100.00
		spi_device_flash_all	0.750s		1	1	100.00
V2	quad_spi	spi_device_flash_all	0.750s		1	1	100.00
V2	dual_spi	spi_device_flash_all	0.750s		1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	2.430s		1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	2.430s		1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	1.053m		1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	1.247m		1	1	100.00
V2	stress_all	spi_device_stress_all	1.215m		1	1	100.00
V2	alert_test	spi_device_alert_test	0.760s		1	1	100.00
V2	intr_test	spi_device_intr_test	0.980s		1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	3.120s		1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	3.120s		1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.110s		1	1	100.00
		spi_device_csr_rw	1.930s		1	1	100.00
		spi_device_csr_aliasing	5.600s		1	1	100.00
		spi_device_same_csr_outstanding	3.010s		1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.110s		1	1	100.00
		spi_device_csr_rw	1.930s		1	1	100.00
		spi_device_csr_aliasing	5.600s		1	1	100.00
		spi_device_same_csr_outstanding	3.010s		1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.180s		1	1	100.00
		spi_device_tl_intg_err	4.960s		1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	4.960s		1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	13.150s		1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.16331192936458691557170836889269028563866696417612888682251421450110274206683
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @    872301 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[12])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @    872301 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @    872301 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[908])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.51309018625797248372595555949071245381514045567164517829773447732958707039243
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @    929825 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xc4d5d3 [110001001101010111010011] vs 0x0 [0])
        UVM_ERROR @    982825 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x19835c [110011000001101011100] vs 0x0 [0])
        UVM_ERROR @   1055825 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x315c82 [1100010101110010000010] vs 0x0 [0])
        UVM_ERROR @   1146825 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xe5c534 [111001011100010100110100] vs 0x0 [0])
        UVM_ERROR @   1151825 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xc4225 [11000100001000100101] vs 0x0 [0])