SPI_HOST Simulation Results

Thursday November 06 2025 19:19:18 UTC

GitHub Revision: 8507ebb

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	25.000s	4.207ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	1.000s	17.184us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	1.000s	29.715us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	2.000s	456.185us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	2.000s	31.822us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	1.000s	120.641us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	1.000s	29.715us	1	1	100.00
		spi_host_csr_aliasing	2.000s	31.822us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	1.000s	46.064us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	1.000s	31.503us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	8.000s	22.265us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	9.000s	418.334us	1	1	100.00
		spi_host_error_cmd	8.000s	16.656us	1	1	100.00
		spi_host_event	20.000s	1.526ms	1	1	100.00
V2	clock_rate	spi_host_speed	8.000s	84.519us	1	1	100.00
V2	speed	spi_host_speed	8.000s	84.519us	1	1	100.00
V2	chip_select_timing	spi_host_speed	8.000s	84.519us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	8.000s	27.299us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	7.000s	30.957us	1	1	100.00
V2	cpol_cpha	spi_host_speed	8.000s	84.519us	1	1	100.00
V2	full_cycle	spi_host_speed	8.000s	84.519us	1	1	100.00
V2	duplex	spi_host_smoke	25.000s	4.207ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	25.000s	4.207ms	1	1	100.00
V2	stress_all	spi_host_stress_all	3.000s	369.636us	1	1	100.00
V2	spien	spi_host_spien	3.000s	2.661ms	1	1	100.00
V2	stall	spi_host_status_stall	52.000s	3.579ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	16.000s	8.094ms	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	9.000s	418.334us	1	1	100.00
V2	alert_test	spi_host_alert_test	1.000s	16.080us	1	1	100.00
V2	intr_test	spi_host_intr_test	2.000s	18.167us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	2.000s	129.066us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	2.000s	129.066us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	1.000s	17.184us	1	1	100.00
		spi_host_csr_rw	1.000s	29.715us	1	1	100.00
		spi_host_csr_aliasing	2.000s	31.822us	1	1	100.00
		spi_host_same_csr_outstanding	2.000s	38.666us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	1.000s	17.184us	1	1	100.00
		spi_host_csr_rw	1.000s	29.715us	1	1	100.00
		spi_host_csr_aliasing	2.000s	31.822us	1	1	100.00
		spi_host_same_csr_outstanding	2.000s	38.666us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	2.000s	87.536us	1	1	100.00
		spi_host_sec_cm	1.000s	134.487us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	2.000s	87.536us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	11.333m	22.693ms	1	1	100.00
		TOTAL			26	26	100.00