SYSRST_CTRL Simulation Results

Thursday November 06 2025 19:19:18 UTC

GitHub Revision: 8507ebb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sysrst_ctrl_smoke	2.850s		1	1	100.00
V1	input_output_inverted	sysrst_ctrl_in_out_inverted	1.530s		1	1	100.00
V1	combo_detect_ec_rst	sysrst_ctrl_combo_detect_ec_rst	1.900s		1	1	100.00
V1	combo_detect_ec_rst_with_pre_cond	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	7.550s		1	1	100.00
V1	csr_hw_reset	sysrst_ctrl_csr_hw_reset	8.200s		1	1	100.00
V1	csr_rw	sysrst_ctrl_csr_rw	2.680s		1	1	100.00
V1	csr_bit_bash	sysrst_ctrl_csr_bit_bash	25.450s		1	1	100.00
V1	csr_aliasing	sysrst_ctrl_csr_aliasing	2.610s		1	1	100.00
V1	csr_mem_rw_with_rand_reset	sysrst_ctrl_csr_mem_rw_with_rand_reset	2.810s		1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sysrst_ctrl_csr_rw	2.680s		1	1	100.00
		sysrst_ctrl_csr_aliasing	2.610s		1	1	100.00
V1		TOTAL			9	9	100.00
V2	combo_detect	sysrst_ctrl_combo_detect	52.120s		1	1	100.00
V2	combo_detect_with_pre_cond	sysrst_ctrl_combo_detect_with_pre_cond	47.090s		1	1	100.00
V2	auto_block_key_outputs	sysrst_ctrl_auto_blk_key_output	3.800s		1	1	100.00
V2	keyboard_input_triggered_interrupt	sysrst_ctrl_edge_detect	2.060s		1	1	100.00
V2	pin_output_keyboard_inversion_control	sysrst_ctrl_pin_override_test	5.010s		1	1	100.00
V2	pin_input_value_accessibility	sysrst_ctrl_pin_access_test	1.360s		1	1	100.00
V2	ec_power_on_reset	sysrst_ctrl_ec_pwr_on_rst	8.870s		1	1	100.00
V2	flash_write_protect_output	sysrst_ctrl_flash_wr_prot_out	1.900s		1	1	100.00
V2	ultra_low_power_test	sysrst_ctrl_ultra_low_pwr	4.740s		0	1	0.00
V2	sysrst_ctrl_feature_disable	sysrst_ctrl_feature_disable	19.580s		1	1	100.00
V2	stress_all	sysrst_ctrl_stress_all	16.490s		1	1	100.00
V2	alert_test	sysrst_ctrl_alert_test	1.640s		1	1	100.00
V2	intr_test	sysrst_ctrl_intr_test	1.290s		1	1	100.00
V2	tl_d_oob_addr_access	sysrst_ctrl_tl_errors	4.960s		1	1	100.00
V2	tl_d_illegal_access	sysrst_ctrl_tl_errors	4.960s		1	1	100.00
V2	tl_d_outstanding_access	sysrst_ctrl_csr_hw_reset	8.200s		1	1	100.00
		sysrst_ctrl_csr_rw	2.680s		1	1	100.00
		sysrst_ctrl_csr_aliasing	2.610s		1	1	100.00
		sysrst_ctrl_same_csr_outstanding	6.400s		1	1	100.00
V2	tl_d_partial_access	sysrst_ctrl_csr_hw_reset	8.200s		1	1	100.00
		sysrst_ctrl_csr_rw	2.680s		1	1	100.00
		sysrst_ctrl_csr_aliasing	2.610s		1	1	100.00
		sysrst_ctrl_same_csr_outstanding	6.400s		1	1	100.00
V2		TOTAL			14	15	93.33
V2S	tl_intg_err	sysrst_ctrl_sec_cm	1.330m		1	1	100.00
		sysrst_ctrl_tl_intg_err	16.010s		1	1	100.00
V2S	sec_cm_bus_integrity	sysrst_ctrl_tl_intg_err	16.010s		1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	sysrst_ctrl_stress_all_with_rand_reset	3.820s		1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	27	96.30

Failure Buckets

• UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 1 failures:
  • Test sysrst_ctrl_ultra_low_pwr has 1 failures.

    • 0.sysrst_ctrl_ultra_low_pwr.100174900882258166610527096868759435313202663879695908751081404847493775214085
      Line 382, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_ultra_low_pwr/latest/run.log

        UVM_ERROR @ 2779400836 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
        UVM_ERROR @ 2779421037 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
        UVM_INFO @ 2779421037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---