UART Simulation Results

Thursday November 06 2025 19:19:18 UTC

GitHub Revision: `8507ebb`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Passing	Total	Pass Rate
V1	smoke	uart_smoke	1.190s	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.670s	1	1	100.00
V1	csr_rw	uart_csr_rw	0.580s	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.880s	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.070s	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	0.880s	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.580s	1	1	100.00
		uart_csr_aliasing	1.070s	1	1	100.00
V1		TOTAL		6	6	100.00
V2	base_random_seq	uart_tx_rx	18.870s	1	1	100.00
V2	parity	uart_smoke	1.190s	1	1	100.00
		uart_tx_rx	18.870s	1	1	100.00
V2	parity_error	uart_intr	43.900s	1	1	100.00
		uart_rx_parity_err	1.089m	1	1	100.00
V2	watermark	uart_tx_rx	18.870s	1	1	100.00
		uart_intr	43.900s	1	1	100.00
V2	fifo_full	uart_fifo_full	1.416m	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	30.680s	1	1	100.00
V2	fifo_reset	uart_fifo_reset	6.320s	1	1	100.00
V2	rx_frame_err	uart_intr	43.900s	1	1	100.00
V2	rx_break_err	uart_intr	43.900s	1	1	100.00
V2	rx_timeout	uart_intr	43.900s	1	1	100.00
V2	perf	uart_perf	2.409m	1	1	100.00
V2	sys_loopback	uart_loopback	3.790s	1	1	100.00
V2	line_loopback	uart_loopback	3.790s	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	5.470s	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.358m	1	1	100.00
V2	tx_overide	uart_tx_ovrd	3.450s	1	1	100.00
V2	rx_oversample	uart_rx_oversample	13.740s	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	1.291m	1	1	100.00
V2	stress_all	uart_stress_all	1.913m	1	1	100.00
V2	alert_test	uart_alert_test	0.820s	1	1	100.00
V2	intr_test	uart_intr_test	0.560s	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.850s	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.850s	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.670s	1	1	100.00
		uart_csr_rw	0.580s	1	1	100.00
		uart_csr_aliasing	1.070s	1	1	100.00
		uart_same_csr_outstanding	0.680s	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.670s	1	1	100.00
		uart_csr_rw	0.580s	1	1	100.00
		uart_csr_aliasing	1.070s	1	1	100.00
		uart_same_csr_outstanding	0.680s	1	1	100.00
V2		TOTAL		17	18	94.44
V2S	tl_intg_err	uart_sec_cm	1.080s	1	1	100.00
		uart_tl_intg_err	1.280s	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.280s	1	1	100.00
V2S		TOTAL		2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	19.490s	1	1	100.00
V3		TOTAL		1	1	100.00
		TOTAL		26	27	96.30

Failure Buckets

UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = *

has 1 failures:

Test uart_noise_filter has 1 failures.

0.uart_noise_filter.39379510321045569930607830912176605181018046475334828164096543038516031722840
Line 72, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

  UVM_ERROR @ 14573234744 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 14584698938 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 14585270362 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 14585984642 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 14586663208 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0