CHIP Simulation Results

Thursday November 06 2025 19:19:18 UTC

GitHub Revision: `8507ebb`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	1.760m	1	1	100.00
		chip_sw_example_rom	1.251m	1	1	100.00
		chip_sw_example_manufacturer	2.578m	1	1	100.00
		chip_sw_example_concurrency	2.674m	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	2.065m	1	1	100.00
V1	csr_rw	chip_csr_rw	3.198m	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	37.218m	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	1.188h	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	1.044m	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	1.188h	1	1	100.00
		chip_csr_rw	3.198m	1	1	100.00
V1	xbar_smoke	xbar_smoke	5.600s	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	5.575m	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	5.575m	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	5.575m	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	5.774m	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	5.774m	1	1	100.00
		chip_sw_uart_tx_rx_idx1	5.594m	1	1	100.00
		chip_sw_uart_tx_rx_idx2	6.516m	1	1	100.00
		chip_sw_uart_tx_rx_idx3	6.709m	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	5.281m	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	5.459m	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	4.770m	1	1	100.00
V1		TOTAL		17	18	94.44
V2	chip_pin_mux	chip_padctrl_attributes	3.167m	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	3.167m	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	3.243m	1	1	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.171m	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.648m	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	2.697m	1	1	100.00
		chip_tap_straps_testunlock0	1.525m	1	1	100.00
		chip_tap_straps_rma	4.014m	1	1	100.00
		chip_tap_straps_prod	20.434m	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	2.950m	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	12.304m	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	8.984m	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	8.984m	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	9.211m	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	32.349m	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	6.093m	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	11.018m	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	57.729m	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.605m	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	9.523m	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.979m	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	25.554m	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.140m	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.942m	1	1	100.00
		chip_sw_clkmgr_jitter	2.422m	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	3.567m	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	8.887m	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	3.785m	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	2.279m	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	3.785m	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	1.703m	1	1	100.00
		chip_sw_aes_smoketest	2.193m	1	1	100.00
		chip_sw_aon_timer_smoketest	3.321m	1	1	100.00
		chip_sw_clkmgr_smoketest	2.527m	1	1	100.00
		chip_sw_csrng_smoketest	2.981m	1	1	100.00
		chip_sw_entropy_src_smoketest	12.179m	1	1	100.00
		chip_sw_gpio_smoketest	3.130m	1	1	100.00
		chip_sw_hmac_smoketest	3.788m	1	1	100.00
		chip_sw_kmac_smoketest	3.306m	1	1	100.00
		chip_sw_otbn_smoketest	10.795m	1	1	100.00
		chip_sw_pwrmgr_smoketest	3.139m	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	4.646m	1	1	100.00
		chip_sw_rv_plic_smoketest	1.902m	1	1	100.00
		chip_sw_rv_timer_smoketest	2.376m	1	1	100.00
		chip_sw_rstmgr_smoketest	1.649m	1	1	100.00
		chip_sw_sram_ctrl_smoketest	1.787m	1	1	100.00
		chip_sw_uart_smoketest	2.267m	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	2.794m	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	5.809m	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	2.232h	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	42.678m	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	2.625m	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	2.572m	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	3.868m	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.949h	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	2.014h	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	40.750s	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	40.750s	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	1.188h	1	1	100.00
		chip_same_csr_outstanding	22.927m	1	1	100.00
		chip_csr_hw_reset	2.065m	1	1	100.00
		chip_csr_rw	3.198m	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	1.188h	1	1	100.00
		chip_same_csr_outstanding	22.927m	1	1	100.00
		chip_csr_hw_reset	2.065m	1	1	100.00
		chip_csr_rw	3.198m	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	5.420s	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	4.890s	1	1	100.00
		xbar_smoke_large_delays	1.006m	1	1	100.00
		xbar_smoke_slow_rsp	46.420s	1	1	100.00
		xbar_random_zero_delays	4.860s	1	1	100.00
		xbar_random_large_delays	41.320s	1	1	100.00
		xbar_random_slow_rsp	4.889m	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	12.820s	1	1	100.00
		xbar_error_and_unmapped_addr	19.840s	1	1	100.00
V2	xbar_error_cases	xbar_error_random	32.490s	1	1	100.00
		xbar_error_and_unmapped_addr	19.840s	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	43.400s	1	1	100.00
		xbar_access_same_device_slow_rsp	4.936m	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	21.160s	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	59.060s	1	1	100.00
		xbar_stress_all_with_error	2.519m	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	10.437m	1	1	100.00
		xbar_stress_all_with_reset_error	41.600s	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	42.678m	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	39.499m	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	43.558m	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	34.347m	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	45.276m	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	44.501m	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	43.464m	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	42.069m	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	24.040s	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	21.930s	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	16.640s	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	21.190s	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	17.970s	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	17.090s	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	28.590s	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	17.170s	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	28.340s	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	24.170s	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	16.460s	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	16.740s	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	16.710s	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	17.240s	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	25.570s	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	18.400s	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	17.100s	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	17.560s	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	17.230s	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	17.630s	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	18.280s	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	19.110s	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	17.170s	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	16.620s	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	18.010s	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	32.801m	1	1	100.00
		rom_e2e_asm_init_dev	42.942m	1	1	100.00
		rom_e2e_asm_init_prod	41.069m	1	1	100.00
		rom_e2e_asm_init_prod_end	41.575m	1	1	100.00
		rom_e2e_asm_init_rma	39.623m	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	40.178m	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	38.285m	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	39.063m	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	42.524m	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	48.051m	0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	48.051m	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	2.597m	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.605m	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	2.045m	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	1.884m	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	12.715m	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	2.054m	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	4.064m	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	6.433m	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	9.094m	1	1	100.00
		chip_plic_all_irqs_10	4.630m	1	1	100.00
		chip_plic_all_irqs_20	6.125m	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	3.259m	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	14.692m	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	5.933m	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	2.760m	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	10.840m	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	14.583m	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	13.978m	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	2.350h	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	3.863m	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	3.139m	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	3.863m	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	8.444m	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	8.444m	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	4.635m	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	4.627m	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	9.691m	1	1	100.00
		chip_sw_aes_idle	1.884m	1	1	100.00
		chip_sw_hmac_enc_idle	2.524m	1	1	100.00
		chip_sw_kmac_idle	2.362m	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	4.340m	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	5.045m	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	5.373m	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	4.891m	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	9.613m	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	6.309m	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	6.135m	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.823m	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.600m	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	7.079m	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.748m	1	1	100.00
		chip_sw_ast_clk_outputs	9.211m	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	11.700m	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.823m	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.600m	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	6.093m	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	11.018m	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	57.729m	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.605m	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	9.523m	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.979m	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	25.554m	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.140m	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.942m	1	1	100.00
		chip_sw_clkmgr_jitter	2.422m	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	2.062m	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	6.910m	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	10.477m	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	52.149m	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	2.080m	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.128m	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	18.126m	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	2.510m	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	5.374m	1	1	100.00
		chip_sw_flash_init_reduced_freq	20.699m	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	3.613h	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	9.211m	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	5.302m	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	4.570m	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	6.433m	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	10.840m	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	14.256m	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	2.278m	0	1	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	5.223m	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	2.586m	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	35.421m	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	2.383m	1	1	100.00
		chip_sw_edn_entropy_reqs	11.731m	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	2.383m	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	14.256m	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	1.593m	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	18.832m	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	10.018m	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	11.018m	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	5.420m	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	6.093m	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	1.055h	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	18.832m	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	3.646m	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	16.276m	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.051m	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	1.055h	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.051m	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.051m	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	4.051m	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.051m	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	6.433m	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	4.727m	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	8.898m	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	6.271m	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	6.271m	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	2.688m	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.979m	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	2.524m	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	1.934m	0	1	0.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	5.140m	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	5.616m	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	6.700m	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	7.208m	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	4.720m	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	16.276m	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	25.554m	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	13.187m	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	12.715m	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	32.971m	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	2.122m	1	1	100.00
		chip_sw_kmac_mode_kmac	2.231m	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.140m	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	16.276m	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	4.415m	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	2.501m	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	27.238m	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	2.362m	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	4.064m	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	2.697m	1	1	100.00
		chip_tap_straps_rma	4.014m	1	1	100.00
		chip_tap_straps_prod	20.434m	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.204m	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	4.415m	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	4.415m	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	4.415m	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	11.518m	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	4.051m	1	1	100.00
		chip_sw_flash_rma_unlocked	1.055h	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.761m	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	9.363m	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	10.156m	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	6.223m	0	1	0.00
		chip_sw_lc_ctrl_transition	4.415m	1	1	100.00
		chip_sw_keymgr_key_derivation	16.276m	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	5.061m	1	1	100.00
		chip_sw_sram_ctrl_execution_main	9.622m	1	1	100.00
		chip_prim_tl_access	4.727m	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	11.700m	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	6.309m	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	6.135m	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.823m	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.600m	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	7.079m	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.748m	1	1	100.00
		chip_tap_straps_dev	2.697m	1	1	100.00
		chip_tap_straps_rma	4.014m	1	1	100.00
		chip_tap_straps_prod	20.434m	1	1	100.00
		chip_rv_dm_lc_disabled	3.344m	0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.218m	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.406m	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.588m	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	1.327m	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	21.760m	1	1	100.00
		chip_rv_dm_lc_disabled	3.344m	0	1	0.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.003h	1	1	100.00
		chip_sw_lc_walkthrough_prod	1.139h	1	1	100.00
		chip_sw_lc_walkthrough_prodend	9.451m	1	1	100.00
		chip_sw_lc_walkthrough_rma	1.059h	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	21.760m	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.202m	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.028m	1	1	100.00
		rom_volatile_raw_unlock	1.196m	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	55.384m	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	57.729m	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	9.691m	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	9.691m	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	9.691m	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	4.715m	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	4.415m	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	18.832m	1	1	100.00
		chip_sw_otbn_mem_scramble	4.715m	1	1	100.00
		chip_sw_keymgr_key_derivation	16.276m	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	4.258m	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.682m	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	18.832m	1	1	100.00
		chip_sw_otbn_mem_scramble	4.715m	1	1	100.00
		chip_sw_keymgr_key_derivation	16.276m	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	4.258m	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.682m	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	4.415m	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	4.289m	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.204m	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.761m	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	9.363m	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	10.156m	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	6.223m	0	1	0.00
		chip_sw_lc_ctrl_transition	4.415m	1	1	100.00
		chip_prim_tl_access	4.727m	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	4.727m	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	17.805m	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	6.071m	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	15.735m	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	4.346m	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	5.543m	0	1	0.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	6.692m	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	17.320m	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	12.406m	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	8.444m	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	10.454m	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	5.144m	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	6.071m	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	3.931m	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	18.029m	0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	4.735m	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	6.492m	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	10.145m	0	1	0.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	11.792m	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	17.204m	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	29.956m	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	2.648m	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	6.433m	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	5.061m	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	5.061m	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	17.204m	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	10.145m	0	1	0.00
		chip_sw_pwrmgr_wdog_reset	5.144m	1	1	100.00
		chip_sw_pwrmgr_smoketest	3.139m	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	5.088m	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	4.613m	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	4.606m	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	14.692m	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	2.659m	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	6.433m	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	14.583m	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	8.152m	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	7.613m	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	3.230m	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	2.682m	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	4.613m	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	4.613m	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	5.100m	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	16.575m	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	5.088m	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	4.245m	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	5.049m	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	4.014m	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	3.344m	0	1	0.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	9.094m	1	1	100.00
		chip_plic_all_irqs_10	4.630m	1	1	100.00
		chip_plic_all_irqs_20	6.125m	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	1.739m	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	2.608m	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	42.678m	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	6.148m	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	3.786m	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	3.038m	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	3.631m	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	4.258m	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.942m	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	8.253m	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	7.926m	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	9.622m	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	6.433m	1	1	100.00
		chip_sw_data_integrity_escalation	8.984m	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	11.792m	1	1	100.00
		chip_sw_sysrst_ctrl_reset	16.617m	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	2.752m	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	3.047m	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	6.644m	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	16.617m	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	16.617m	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	39.649m	1	1	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	39.649m	1	1	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	5.542m	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	48.051m	0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	1.696m	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	2.906m	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	4.778m	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	4.869m	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	17.002m	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.462h	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	29.803m	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	2.332m	1	1	100.00
V2		TOTAL		233	275	84.73
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	3.349m	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	1.978m	1	1	100.00
V2S		TOTAL		2	2	100.00
V3	chip_sw_coremark	chip_sw_coremark	2.646h	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	18.613m	1	1	100.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	20.124m	1	1	100.00
		rom_e2e_jtag_debug_dev	20.174m	1	1	100.00
		rom_e2e_jtag_debug_rma	11.291m	0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	4.430m	1	1	100.00
		rom_e2e_jtag_inject_dev	3.510m	1	1	100.00
		rom_e2e_jtag_inject_rma	3.583m	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	10.920s	0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	8.416m	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	4.779m	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	19.111m	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	14.721m	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.794m	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	9.848m	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	2.493m	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	2.974m	0	1	0.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	3.908m	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	4.454m	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	17.204m	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	20.124m	1	1	100.00
		rom_e2e_jtag_debug_dev	20.174m	1	1	100.00
		rom_e2e_jtag_debug_rma	11.291m	0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	4.629m	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	6.433m	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.548h	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.548h	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	3.040m	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	5.774m	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	53.921m	1	1	100.00
V3		TOTAL		20	23	86.96
	Unmapped tests	chip_sival_flash_info_access	2.529m	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	6.440m	1	1	100.00
		chip_sw_otp_ctrl_rot_auth_config	29.880m	0	1	0.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	2.966m	1	1	100.00
		chip_sw_otp_ctrl_descrambling	3.399m	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	3.381m	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	10.751s	0	1	0.00
		chip_sw_flash_ctrl_write_clear	3.069m	1	1	100.00
		TOTAL		278	326	85.28

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.33351389171006886161474660062613459471491975989019244842185318133173033703231
    Line 500, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.92987256918528486903134242316669242555054644765528663957992769084783083308521
    Line 497, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.57681946415302831777377628077909968347733640037422898020542636304096682333772
    Line 493, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.55215693777956933662735865499838576487529710278932126253047102525436223514373
    Line 469, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.37923623116259002329346022681156369145299542006622623664981133104891648250449
    Line 476, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.41230175914896365178308220669324802452556945072972573619131825539831185651985
    Line 512, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.65631650967610845721434608930976761384106535812235287690583476850458364604492
    Line 474, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.62869647096064853249019267177322604839931328542332007560402703100502721133299
    Line 489, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.78833680567844463732530277995242145111119175740249803721008679715903242711332
    Line 476, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.29814696745920916900350881535661787869710800040582606496406019955625078527828
    Line 485, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(rstreqs[*] && (reset_cause == HwReq))' has 3 failures:
- Test chip_sw_pwrmgr_random_sleep_all_reset_reqs has 1 failures.
  - 0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.37390426048583410058144965893341284101261468111093180724287977911575927167181
    Line 433, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest/run.log
```
      Offending '(rstreqs[1] && (reset_cause == HwReq))'
  UVM_ERROR @ 12053.506500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
  UVM_INFO @ 12053.506500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_pwrmgr_deep_sleep_por_reset has 1 failures.
  - 0.chip_sw_pwrmgr_deep_sleep_por_reset.80901885545690669111876309843164316646649038678553962708261931452390264369970
    Line 413, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_por_reset/latest/run.log
```
      Offending '(rstreqs[0] && (reset_cause == HwReq))'
  UVM_ERROR @ 6771.592000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
  UVM_INFO @ 6771.592000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_pwrmgr_random_sleep_power_glitch_reset has 1 failures.
  - 0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.87789660316285108045605146004167662387977316586954880819530989611704698515615
    Line 459, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest/run.log
```
      Offending '(rstreqs[1] && (reset_cause == HwReq))'
  UVM_ERROR @ 21271.925000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
  UVM_INFO @ 21271.925000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.43362649133533353756744919471441168280540754757342246823757425416883029884982
    Line 488, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.103991257697937606131902389626601438002078375401517043937049976769089452310926
    Line 504, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.19700111187957310777608656330158663054409670709210453129802325069947546345937
    Line 478, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' has 2 failures:
- Test chip_sw_otp_ctrl_escalation has 1 failures.
  - 0.chip_sw_otp_ctrl_escalation.98775929916305366731663020658342742655159493608172945317393783540166704439554
    Line 398, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_escalation/latest/run.log
```
      Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
  UVM_ERROR @ 2873.011792 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
  UVM_INFO @ 2873.011792 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_csrng_fuse_en_sw_app_read_test has 1 failures.
  - 0.chip_sw_csrng_fuse_en_sw_app_read_test.22412754255955452294855342855963462623334366327128136757919647769814623379783
    Line 402, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
      Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
  UVM_ERROR @ 2849.502264 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
  UVM_INFO @ 2849.502264 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 2 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.106440145588123191523405901246804752523708363578185223942537399140169849736261
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 1.676s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.13432047788063614181198035253149254358561848146395193198783320532818107081190
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 0.166s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.33948904232558358746950494880156617773610462309830763090946983613910931845201
    Line 522, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.102862468005556815788354602283575030196438729835524386617644831079870930018518
    Line 491, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.46697492464006778288351242362394894376674573164162105464070747762074032144271
    Line 559, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.76119610685167846258499105216426283205605053407988427458828726794900869165320
    Line 494, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.11416061623265307968369474992115668457392828246722827839127880086821393774204
    Line 419, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3070.326781 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 3070.326781 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to * has 1 failures:
- Test chip_sw_otp_ctrl_lc_signals_rma has 1 failures.
  - 0.chip_sw_otp_ctrl_lc_signals_rma.58777305950246135665365585181774742840618347135000208504474371479931626898386
    Line 423, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_rma/latest/run.log
```
  UVM_ERROR @ 6768.169300 us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to 0x0
  UVM_INFO @ 6768.169300 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_rot_auth_config_test_sim_dv(sw/device/tests/otp_ctrl_rot_auth_config_test.c:22)] CHECK-STATUS-fail: @@@:* = ErrorError has 1 failures:
- Test chip_sw_otp_ctrl_rot_auth_config has 1 failures.
  - 0.chip_sw_otp_ctrl_rot_auth_config.49399506237393557819916701215523632788852051082876989382264022086118533907094
    Line 461, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_rot_auth_config/latest/run.log
```
  UVM_ERROR @ 22529.866013 us: (sw_logger_if.sv:526) [otp_ctrl_rot_auth_config_test_sim_dv(sw/device/tests/otp_ctrl_rot_auth_config_test.c:22)] CHECK-STATUS-fail: @@@:0 = ErrorError
  UVM_INFO @ 22529.866013 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@102742) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.7456555309351007537228518997539274488486910192438282120780558253167202818857
Line 438, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 4381.938632 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@102742) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h0  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4381.938632 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 1 failures.
  - 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.81850927518526933797917820202305680526370180694736566171673548245223156279260
    Line 420, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  UVM_ERROR @ 34905.699382 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 34905.699382 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.51188309109722252331825788972173901097402620619430215433724102540809383617667
    Line 390, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 2540.931120 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 42!
  UVM_INFO @ 2540.931120 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.12013293822886669162635326394008995906181887585127707851896837459458053889084
    Line 390, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3015.840016 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 3015.840016 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job timed out after * minutes has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_pings has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_pings.69322293734613114667758126647474660993350524387397797116746209446422629145424
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest/run.log
```
  Job timed out after 240 minutes
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: *. has 1 failures:
- Test chip_sw_hmac_oneshot has 1 failures.
  - 0.chip_sw_hmac_oneshot.7913743034942065407247950890345326731449468220750705096783854212705980771620
    Line 394, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_oneshot/latest/run.log
```
  UVM_ERROR @ 2748.772028 us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: 8000534a.
  UVM_INFO @ 2748.772028 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33050) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.56297990793930480603631939109266291966587693142478678720342538134864241322233
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2271.964412 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33050) { a_addr: 'h1061c  a_data: 'h19538a5  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2b  a_opcode: 'h4  a_user: 'h1a207  d_param: 'h0  d_source: 'h2b  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2271.964412 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_vseq.sv:642) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 1 failures:
- Test chip_rv_dm_lc_disabled has 1 failures.
  - 0.chip_rv_dm_lc_disabled.11867056438099594409153321293236413963251645418832094433891620128632452755002
    Line 250, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log
```
  UVM_ERROR @ 9636.500752 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x104a8 read out mismatch
  UVM_INFO @ 9636.500752 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.102130421059230959901277963992431202015864584699889115679128929108959781723601
    Line 395, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 3029.141500 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH3 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3029.141500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.52166157590893894798000981949026296549818958980385510101515195375411734492251
    Line 411, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 2920.430000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 2920.430000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.64561137954365458629590310122205993136644311239296888343600361231521025666040
    Line 425, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 19162.584540 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 19162.584540 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.60406431509586295333118994096077464901465504800720743632214781489009161724350
    Line 450, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.20008219574846591080405500072120025370862437079790016848872990623730710730734
    Line 434, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred! has 1 failures:
- Test rom_e2e_jtag_debug_rma has 1 failures.
  - 0.rom_e2e_jtag_debug_rma.66699777724551010611146522542087334797292230070929563912990372915242706714781
    Line 416, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log
```
  UVM_FATAL @ 13857.268877 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 13857.268877 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32196) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

0.chip_csr_mem_rw_with_rand_reset.67048652242207171976369961525048949309078618108231390988743383990277123984841
Line 221, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2403.846968 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32196) { a_addr: 'h105e4  a_data: 'he78c97df  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hf  a_opcode: 'h4  a_user: 'h19eec  d_param: 'h0  d_source: 'hf  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2403.846968 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---