ADC_CTRL Simulation Results

Monday November 10 2025 19:24:23 UTC

GitHub Revision: 3c586cb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	9.810s		1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	1.950s		1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.170s		1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.134m		1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	1.370s		1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	0.900s		1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.170s		1	1	100.00
		adc_ctrl_csr_aliasing	1.370s		1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	3.814m		1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	12.528m		1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	4.234m		1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	1.619m		1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	6.944m		1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	2.546m		1	1	100.00
V2	filters_both	adc_ctrl_filters_both	10.074m		1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	8.073m		0	1	0.00
V2	poweron_counter	adc_ctrl_poweron_counter	2.460s		1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	19.730s		1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	1.699m		1	1	100.00
V2	stress_all	adc_ctrl_stress_all	3.276m		1	1	100.00
V2	alert_test	adc_ctrl_alert_test	0.890s		1	1	100.00
V2	intr_test	adc_ctrl_intr_test	0.730s		1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	1.350s		1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	1.350s		1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	1.950s		1	1	100.00
		adc_ctrl_csr_rw	1.170s		1	1	100.00
		adc_ctrl_csr_aliasing	1.370s		1	1	100.00
		adc_ctrl_same_csr_outstanding	5.700s		1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	1.950s		1	1	100.00
		adc_ctrl_csr_rw	1.170s		1	1	100.00
		adc_ctrl_csr_aliasing	1.370s		1	1	100.00
		adc_ctrl_same_csr_outstanding	5.700s		1	1	100.00
V2		TOTAL			15	16	93.75
V2S	tl_intg_err	adc_ctrl_sec_cm	5.880s		1	1	100.00
		adc_ctrl_tl_intg_err	7.380s		1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	7.380s		1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	5.940s		1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			24	25	96.00

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test adc_ctrl_clock_gating has 1 failures.

    • 0.adc_ctrl_clock_gating.90704445823385719705864244637410482880157493162073488622755751442365554085145
      Line 165, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/0.adc_ctrl_clock_gating/latest/run.log

        UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---