HMAC Simulation Results

Monday November 10 2025 19:24:23 UTC

GitHub Revision: 3c586cb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 4.910s 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 0.870s 1 1 100.00
V1 csr_rw hmac_csr_rw 0.650s 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 4.380s 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 6.200s 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 1.550s 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 0.650s 1 1 100.00
hmac_csr_aliasing 6.200s 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 10.090s 1 1 100.00
V2 back_pressure hmac_back_pressure 15.660s 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 8.110s 1 1 100.00
hmac_test_sha384_vectors 6.288m 1 1 100.00
hmac_test_sha512_vectors 5.484m 1 1 100.00
hmac_test_hmac256_vectors 6.880s 1 1 100.00
hmac_test_hmac384_vectors 7.630s 1 1 100.00
hmac_test_hmac512_vectors 10.830s 1 1 100.00
V2 burst_wr hmac_burst_wr 13.760s 1 1 100.00
V2 datapath_stress hmac_datapath_stress 6.461m 1 1 100.00
V2 error hmac_error 17.930s 1 1 100.00
V2 wipe_secret hmac_wipe_secret 26.750s 1 1 100.00
V2 save_and_restore hmac_smoke 4.910s 1 1 100.00
hmac_long_msg 10.090s 1 1 100.00
hmac_back_pressure 15.660s 1 1 100.00
hmac_datapath_stress 6.461m 1 1 100.00
hmac_burst_wr 13.760s 1 1 100.00
hmac_stress_all 10.527m 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 4.910s 1 1 100.00
hmac_long_msg 10.090s 1 1 100.00
hmac_back_pressure 15.660s 1 1 100.00
hmac_datapath_stress 6.461m 1 1 100.00
hmac_wipe_secret 26.750s 1 1 100.00
hmac_test_sha256_vectors 8.110s 1 1 100.00
hmac_test_sha384_vectors 6.288m 1 1 100.00
hmac_test_sha512_vectors 5.484m 1 1 100.00
hmac_test_hmac256_vectors 6.880s 1 1 100.00
hmac_test_hmac384_vectors 7.630s 1 1 100.00
hmac_test_hmac512_vectors 10.830s 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 4.910s 1 1 100.00
hmac_long_msg 10.090s 1 1 100.00
hmac_back_pressure 15.660s 1 1 100.00
hmac_datapath_stress 6.461m 1 1 100.00
hmac_burst_wr 13.760s 1 1 100.00
hmac_error 17.930s 1 1 100.00
hmac_wipe_secret 26.750s 1 1 100.00
hmac_test_sha256_vectors 8.110s 1 1 100.00
hmac_test_sha384_vectors 6.288m 1 1 100.00
hmac_test_sha512_vectors 5.484m 1 1 100.00
hmac_test_hmac256_vectors 6.880s 1 1 100.00
hmac_test_hmac384_vectors 7.630s 1 1 100.00
hmac_test_hmac512_vectors 10.830s 1 1 100.00
hmac_stress_all 10.527m 1 1 100.00
V2 stress_all hmac_stress_all 10.527m 1 1 100.00
V2 alert_test hmac_alert_test 0.560s 1 1 100.00
V2 intr_test hmac_intr_test 0.650s 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.310s 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.310s 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 0.870s 1 1 100.00
hmac_csr_rw 0.650s 1 1 100.00
hmac_csr_aliasing 6.200s 1 1 100.00
hmac_same_csr_outstanding 1.340s 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 0.870s 1 1 100.00
hmac_csr_rw 0.650s 1 1 100.00
hmac_csr_aliasing 6.200s 1 1 100.00
hmac_same_csr_outstanding 1.340s 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 0.880s 1 1 100.00
hmac_tl_intg_err 2.360s 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 2.360s 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 4.910s 1 1 100.00
V3 stress_reset hmac_stress_reset 4.780s 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 21.470s 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 2.210s 1 1 100.00
TOTAL 28 28 100.00