I2C Simulation Results

Monday November 10 2025 19:24:23 UTC

GitHub Revision: 3c586cb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	1.077m		1	1	100.00
V1	target_smoke	i2c_target_smoke	14.550s		1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.880s		1	1	100.00
V1	csr_rw	i2c_csr_rw	0.780s		1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	2.070s		1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.020s		1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	0.850s		1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.780s		1	1	100.00
		i2c_csr_aliasing	1.020s		1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	1.380s		0	1	0.00
V2	host_stress_all	i2c_host_stress_all	12.630m		0	1	0.00
V2	host_maxperf	i2c_host_perf	2.729m		1	1	100.00
V2	host_override	i2c_host_override	0.630s		1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	3.578m		1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	37.920s		1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.180s		1	1	100.00
		i2c_host_fifo_fmt_empty	10.810s		1	1	100.00
		i2c_host_fifo_reset_rx	4.780s		1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	1.222m		1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	11.180s		1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	0.640s		0	1	0.00
V2	target_glitch	i2c_target_glitch	2.340s		0	1	0.00
V2	target_stress_all	i2c_target_stress_all	1.028m		1	1	100.00
V2	target_maxperf	i2c_target_perf	2.330s		1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	9.130s		1	1	100.00
		i2c_target_intr_smoke	3.330s		1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.490s		1	1	100.00
		i2c_target_fifo_reset_tx	0.940s		1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	15.220s		1	1	100.00
		i2c_target_stress_rd	9.130s		1	1	100.00
		i2c_target_intr_stress_wr	9.270s		1	1	100.00
V2	target_timeout	i2c_target_timeout	5.170s		1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	4.370s		0	1	0.00
V2	bad_address	i2c_target_bad_addr	4.330s		1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	17.340s		0	1	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.410s		1	1	100.00
		i2c_target_fifo_watermarks_tx	1.230s		1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	2.729m		1	1	100.00
		i2c_host_perf_precise	2.910s		1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	11.180s		1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	2.150s		1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.130s		1	1	100.00
		i2c_target_nack_acqfull_addr	2.000s		1	1	100.00
		i2c_target_nack_txstretch	1.220s		0	1	0.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	4.940s		1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	1.650s		1	1	100.00
V2	alert_test	i2c_alert_test	0.770s		1	1	100.00
V2	intr_test	i2c_intr_test	0.750s		1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.170s		1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.170s		1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.880s		1	1	100.00
		i2c_csr_rw	0.780s		1	1	100.00
		i2c_csr_aliasing	1.020s		1	1	100.00
		i2c_same_csr_outstanding	1.050s		1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.880s		1	1	100.00
		i2c_csr_rw	0.780s		1	1	100.00
		i2c_csr_aliasing	1.020s		1	1	100.00
		i2c_same_csr_outstanding	1.050s		1	1	100.00
V2		TOTAL			31	38	81.58
V2S	tl_intg_err	i2c_tl_intg_err	1.410s		1	1	100.00
		i2c_sec_cm	0.940s		1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	1.410s		1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	14.080s		0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	0.900s		0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	8.950s		0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			40	50	80.00

Failure Buckets

• UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 3 failures:

  • Test i2c_host_error_intr has 1 failures.

    • 0.i2c_host_error_intr.33791690385220078325310216503901577108749695030797816105743154267922690632584
      Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

        UVM_ERROR @  72313803 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @  72313803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.104649681969957954066045251664443076007357117447676746740971091377141065408454
      Line 100, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1385327055 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @ 1385327055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_host_mode_toggle has 1 failures.

    • 0.i2c_host_mode_toggle.60543677975056471203094700817739502819139147158649112005807960773941377529640
      Line 78, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

        UVM_ERROR @  22817951 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @  22817951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

  • Test i2c_host_stress_all has 1 failures.

    • 0.i2c_host_stress_all.85310932083171679477115978489147940604999296910915138507546760079620637994189
      Line 112, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

        UVM_ERROR @ 73890140297 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
        ----------------------------------------------------
        Name            Type                Size  Value
        ----------------------------------------------------
        mon_dut_item    i2c_item            -     @632820
      

• UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_target_glitch has 1 failures.

    • 0.i2c_target_glitch.54983791325419949807988285380229475892823821247765290072309445417299588381628
      Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

        UVM_ERROR @ 530278136 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
        UVM_INFO @ 530278136 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 1 failures:

  • Test i2c_target_stretch has 1 failures.

    • 0.i2c_target_stretch.101898943558754418580115785734321382494679246931993661430877764458551045627508
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stretch/latest/run.log

        UVM_FATAL @ 10045309528 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
        UVM_INFO @ 10045309528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.103429175843638595697820279154339863607190181728482925820333125426804698154334
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @  94690093 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 165 [0xa5])
        UVM_INFO @  94690093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:

  • Test i2c_target_hrst has 1 failures.

    • 0.i2c_target_hrst.73711333859022852999215906176485886116721015463402911498563178710793059922631
      Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log

        UVM_FATAL @ 10006389504 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
        UVM_INFO @ 10006389504 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.110673933571076004611896917931486353247464872596681637121552956204613354471550
      Line 89, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 419305714 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 419305714 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 1 failures:

  • Test i2c_target_nack_txstretch has 1 failures.

    • 0.i2c_target_nack_txstretch.58863331104487387353973040321150909572102441442755612370436278470523101826460
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log

        UVM_ERROR @ 716465191 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
        UVM_INFO @ 716465191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---