KMAC/UNMASKED Simulation Results

Monday November 10 2025 19:24:23 UTC

GitHub Revision: 3c586cb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	27.080s		1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.110s		1	1	100.00
V1	csr_rw	kmac_csr_rw	0.990s		1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	13.910s		1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	5.280s		1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	1.270s		1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	0.990s		1	1	100.00
		kmac_csr_aliasing	5.280s		1	1	100.00
V1	mem_walk	kmac_mem_walk	0.670s		1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.200s		1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	9.562m		1	1	100.00
V2	burst_write	kmac_burst_write	4.283m		1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	25.039m		1	1	100.00
		kmac_test_vectors_sha3_256	27.891m		1	1	100.00
		kmac_test_vectors_sha3_384	13.385m		1	1	100.00
		kmac_test_vectors_sha3_512	8.842m		1	1	100.00
		kmac_test_vectors_shake_128	1.949m		1	1	100.00
		kmac_test_vectors_shake_256	1.355m		1	1	100.00
		kmac_test_vectors_kmac	1.660s		1	1	100.00
		kmac_test_vectors_kmac_xof	1.700s		1	1	100.00
V2	sideload	kmac_sideload	2.528m		1	1	100.00
V2	app	kmac_app	1.799m		1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	2.280m		1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	1.289m		1	1	100.00
V2	error	kmac_error	2.409m		1	1	100.00
V2	key_error	kmac_key_error	3.430s		1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	3.230s		1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	7.590s		1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	32.290s		1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	38.230s		1	1	100.00
V2	lc_escalation	kmac_lc_escalation	1.500s		1	1	100.00
V2	stress_all	kmac_stress_all	2.348m		1	1	100.00
V2	intr_test	kmac_intr_test	0.760s		1	1	100.00
V2	alert_test	kmac_alert_test	1.110s		1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.010s		1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.010s		1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.110s		1	1	100.00
		kmac_csr_rw	0.990s		1	1	100.00
		kmac_csr_aliasing	5.280s		1	1	100.00
		kmac_same_csr_outstanding	1.210s		1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.110s		1	1	100.00
		kmac_csr_rw	0.990s		1	1	100.00
		kmac_csr_aliasing	5.280s		1	1	100.00
		kmac_same_csr_outstanding	1.210s		1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.780s		1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.780s		1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.780s		1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.780s		1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	4.380s		1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	47.160s		1	1	100.00
		kmac_tl_intg_err	2.170s		1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	2.170s		1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.500s		1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	27.080s		1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	2.528m		1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.780s		1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	47.160s		1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	47.160s		1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	47.160s		1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	27.080s		1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.500s		1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	47.160s		1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	14.920s		1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	27.080s		1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	41.150s		0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			39	40	97.50

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:840) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 1 failures:
  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.38550541710865632055448462842090459376404182873923268666914830904120335702945
      Line 229, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5092595589 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
        UVM_INFO @ 5092595589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---