PATTGEN Simulation Results

Monday November 10 2025 19:24:23 UTC

GitHub Revision: 3c586cb

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	1.000s	32.689us	1	1	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	1.000s	104.078us	1	1	100.00
V1	csr_rw	pattgen_csr_rw	2.000s	15.716us	1	1	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	4.000s	1.111ms	1	1	100.00
V1	csr_aliasing	pattgen_csr_aliasing	2.000s	16.300us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	1.000s	24.363us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	2.000s	15.716us	1	1	100.00
		pattgen_csr_aliasing	2.000s	16.300us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	perf	pattgen_perf	1.067m	2.692ms	1	1	100.00
V2	cnt_rollover	cnt_rollover	33.000s	8.247ms	1	1	100.00
V2	error	pattgen_error	1.000s	41.950us	1	1	100.00
V2	stress_all	pattgen_stress_all	1.000s	39.738us	1	1	100.00
V2	alert_test	pattgen_alert_test	1.000s	25.170us	1	1	100.00
V2	intr_test	pattgen_intr_test	1.000s	14.220us	1	1	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	2.000s	102.696us	1	1	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	2.000s	102.696us	1	1	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	1.000s	104.078us	1	1	100.00
		pattgen_csr_rw	2.000s	15.716us	1	1	100.00
		pattgen_csr_aliasing	2.000s	16.300us	1	1	100.00
		pattgen_same_csr_outstanding	1.000s	110.450us	1	1	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	1.000s	104.078us	1	1	100.00
		pattgen_csr_rw	2.000s	15.716us	1	1	100.00
		pattgen_csr_aliasing	2.000s	16.300us	1	1	100.00
		pattgen_same_csr_outstanding	1.000s	110.450us	1	1	100.00
V2		TOTAL			8	8	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	2.000s	99.670us	1	1	100.00
		pattgen_sec_cm	1.000s	146.891us	1	1	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	2.000s	99.670us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	17.000s	56.160ms	1	1	100.00
V3		TOTAL			1	1	100.00
	Unmapped tests	pattgen_inactive_level	15.000s	10.195ms	0	1	0.00
		TOTAL			17	18	94.44

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15) has 1 failures:
  • Test pattgen_inactive_level has 1 failures.

    • 0.pattgen_inactive_level.80758004766793163231919468106545448216551229898089376805306655175214801723143
      Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_inactive_level/latest/run.log

        UVM_FATAL @ 10194831514 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x82eacfd0, Comparison=CompareOpEq, exp_data=0x0, call_count=15)
        UVM_INFO @ 10194831514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---