3c586cb| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rv_dm_smoke | 1.610s | 1 | 1 | 100.00 | |
| V1 | jtag_dtm_csr_hw_reset | rv_dm_jtag_dtm_csr_hw_reset | 0.700s | 1 | 1 | 100.00 | |
| V1 | jtag_dtm_csr_rw | rv_dm_jtag_dtm_csr_rw | 0.750s | 1 | 1 | 100.00 | |
| V1 | jtag_dtm_csr_bit_bash | rv_dm_jtag_dtm_csr_bit_bash | 20.620s | 1 | 1 | 100.00 | |
| V1 | jtag_dtm_csr_aliasing | rv_dm_jtag_dtm_csr_aliasing | 0.940s | 1 | 1 | 100.00 | |
| V1 | jtag_dmi_csr_hw_reset | rv_dm_jtag_dmi_csr_hw_reset | 3.660s | 1 | 1 | 100.00 | |
| V1 | jtag_dmi_csr_rw | rv_dm_jtag_dmi_csr_rw | 12.650s | 1 | 1 | 100.00 | |
| V1 | jtag_dmi_csr_bit_bash | rv_dm_jtag_dmi_csr_bit_bash | 6.520s | 1 | 1 | 100.00 | |
| V1 | jtag_dmi_csr_aliasing | rv_dm_jtag_dmi_csr_aliasing | 14.810s | 1 | 1 | 100.00 | |
| V1 | jtag_dmi_cmderr_busy | rv_dm_cmderr_busy | 1.010s | 1 | 1 | 100.00 | |
| V1 | jtag_dmi_cmderr_not_supported | rv_dm_cmderr_not_supported | 1.570s | 1 | 1 | 100.00 | |
| V1 | cmderr_exception | rv_dm_cmderr_exception | 0.810s | 1 | 1 | 100.00 | |
| V1 | mem_tl_access_resuming | rv_dm_mem_tl_access_resuming | 0.780s | 1 | 1 | 100.00 | |
| V1 | mem_tl_access_halted | rv_dm_mem_tl_access_halted | 1.220s | 1 | 1 | 100.00 | |
| V1 | cmderr_halt_resume | rv_dm_cmderr_halt_resume | 1.320s | 1 | 1 | 100.00 | |
| V1 | dataaddr_rw_access | rv_dm_dataaddr_rw_access | 0.660s | 1 | 1 | 100.00 | |
| V1 | halt_resume | rv_dm_halt_resume_whereto | 1.500s | 1 | 1 | 100.00 | |
| V1 | progbuf_busy | rv_dm_cmderr_busy | 1.010s | 1 | 1 | 100.00 | |
| V1 | abstractcmd_status | rv_dm_abstractcmd_status | 1.450s | 1 | 1 | 100.00 | |
| V1 | progbuf_read_write_execute | rv_dm_progbuf_read_write_execute | 1.030s | 1 | 1 | 100.00 | |
| V1 | progbuf_exception | rv_dm_cmderr_exception | 0.810s | 1 | 1 | 100.00 | |
| V1 | rom_read_access | rv_dm_rom_read_access | 0.740s | 1 | 1 | 100.00 | |
| V1 | csr_hw_reset | rv_dm_csr_hw_reset | 1.630s | 1 | 1 | 100.00 | |
| V1 | csr_rw | rv_dm_csr_rw | 1.780s | 1 | 1 | 100.00 | |
| V1 | csr_bit_bash | rv_dm_csr_bit_bash | 43.300s | 1 | 1 | 100.00 | |
| V1 | csr_aliasing | rv_dm_csr_aliasing | 47.510s | 1 | 1 | 100.00 | |
| V1 | csr_mem_rw_with_rand_reset | rv_dm_csr_mem_rw_with_rand_reset | 0.750s | 0 | 1 | 0.00 | |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_dm_csr_aliasing | 47.510s | 1 | 1 | 100.00 | |
| rv_dm_csr_rw | 1.780s | 1 | 1 | 100.00 | |||
| V1 | mem_walk | rv_dm_mem_walk | 0.660s | 1 | 1 | 100.00 | |
| V1 | mem_partial_access | rv_dm_mem_partial_access | 0.760s | 1 | 1 | 100.00 | |
| V1 | TOTAL | 26 | 27 | 96.30 | |||
| V2 | idcode | rv_dm_smoke | 1.610s | 1 | 1 | 100.00 | |
| V2 | jtag_dtm_hard_reset | rv_dm_jtag_dtm_hard_reset | 0.790s | 1 | 1 | 100.00 | |
| V2 | jtag_dtm_idle_hint | rv_dm_jtag_dtm_idle_hint | 0.740s | 1 | 1 | 100.00 | |
| V2 | jtag_dmi_failed_op | rv_dm_dmi_failed_op | 0.650s | 1 | 1 | 100.00 | |
| V2 | jtag_dmi_dm_inactive | rv_dm_jtag_dmi_dm_inactive | 3.310s | 1 | 1 | 100.00 | |
| V2 | sba | rv_dm_sba_tl_access | 9.752m | 0 | 1 | 0.00 | |
| rv_dm_delayed_resp_sba_tl_access | 8.636m | 0 | 1 | 0.00 | |||
| V2 | bad_sba | rv_dm_bad_sba_tl_access | 2.289m | 0 | 1 | 0.00 | |
| V2 | sba_autoincrement | rv_dm_autoincr_sba_tl_access | 4.388m | 0 | 1 | 0.00 | |
| V2 | jtag_dmi_debug_disabled | rv_dm_jtag_dmi_debug_disabled | 1.130s | 1 | 1 | 100.00 | |
| V2 | sba_debug_disabled | rv_dm_sba_debug_disabled | 2.320s | 1 | 1 | 100.00 | |
| V2 | ndmreset_req | rv_dm_ndmreset_req | 0.730s | 1 | 1 | 100.00 | |
| V2 | hart_unavail | rv_dm_hart_unavail | 0.840s | 1 | 1 | 100.00 | |
| V2 | tap_ctrl_transitions | rv_dm_tap_fsm | 6.100s | 0 | 1 | 0.00 | |
| rv_dm_tap_fsm_rand_reset | 0.680s | 0 | 1 | 0.00 | |||
| V2 | hartsel_warl | rv_dm_hartsel_warl | 0.710s | 1 | 1 | 100.00 | |
| V2 | stress_all | rv_dm_stress_all | 4.620s | 1 | 1 | 100.00 | |
| V2 | alert_test | rv_dm_alert_test | 0.750s | 1 | 1 | 100.00 | |
| V2 | tl_d_oob_addr_access | rv_dm_tl_errors | 0.680s | 0 | 1 | 0.00 | |
| V2 | tl_d_illegal_access | rv_dm_tl_errors | 0.680s | 0 | 1 | 0.00 | |
| V2 | tl_d_outstanding_access | rv_dm_csr_aliasing | 47.510s | 1 | 1 | 100.00 | |
| rv_dm_csr_hw_reset | 1.630s | 1 | 1 | 100.00 | |||
| rv_dm_csr_rw | 1.780s | 1 | 1 | 100.00 | |||
| rv_dm_same_csr_outstanding | 2.900s | 1 | 1 | 100.00 | |||
| V2 | tl_d_partial_access | rv_dm_csr_aliasing | 47.510s | 1 | 1 | 100.00 | |
| rv_dm_csr_hw_reset | 1.630s | 1 | 1 | 100.00 | |||
| rv_dm_csr_rw | 1.780s | 1 | 1 | 100.00 | |||
| rv_dm_same_csr_outstanding | 2.900s | 1 | 1 | 100.00 | |||
| V2 | TOTAL | 12 | 19 | 63.16 | |||
| V2S | tl_intg_err | rv_dm_sec_cm | 1.370s | 1 | 1 | 100.00 | |
| rv_dm_tl_intg_err | 12.510s | 1 | 1 | 100.00 | |||
| V2S | sec_cm_bus_integrity | rv_dm_tl_intg_err | 12.510s | 1 | 1 | 100.00 | |
| V2S | sec_cm_lc_hw_debug_en_intersig_mubi | rv_dm_sba_debug_disabled | 2.320s | 1 | 1 | 100.00 | |
| rv_dm_debug_disabled | 0.840s | 1 | 1 | 100.00 | |||
| V2S | sec_cm_lc_dft_en_intersig_mubi | rv_dm_sba_debug_disabled | 2.320s | 1 | 1 | 100.00 | |
| rv_dm_debug_disabled | 0.840s | 1 | 1 | 100.00 | |||
| V2S | sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi | rv_dm_smoke | 1.610s | 1 | 1 | 100.00 | |
| V2S | sec_cm_dm_en_ctrl_lc_gated | rv_dm_buffered_enable | 1.030s | 1 | 1 | 100.00 | |
| V2S | sec_cm_sba_tl_lc_gate_fsm_sparse | rv_dm_sparse_lc_gate_fsm | 0.780s | 1 | 1 | 100.00 | |
| V2S | sec_cm_mem_tl_lc_gate_fsm_sparse | rv_dm_sparse_lc_gate_fsm | 0.780s | 1 | 1 | 100.00 | |
| V2S | sec_cm_exec_ctrl_mubi | rv_dm_buffered_enable | 1.030s | 1 | 1 | 100.00 | |
| V2S | TOTAL | 5 | 5 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_dm_stress_all_with_rand_reset | 0.700s | 0 | 1 | 0.00 | |
| V3 | TOTAL | 0 | 1 | 0.00 | |||
| Unmapped tests | rv_dm_scanmode | 0.630s | 1 | 1 | 100.00 | ||
| TOTAL | 44 | 53 | 83.02 |
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:
Test rv_dm_sba_tl_access has 1 failures.
0.rv_dm_sba_tl_access.1611783489058910766139593885415806318884489014017161581792540651754287516664
Line 83, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_sba_tl_access/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_delayed_resp_sba_tl_access has 1 failures.
0.rv_dm_delayed_resp_sba_tl_access.10544327806770794161361542071245847616540926239853705333258684774168867360420
Line 83, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_delayed_resp_sba_tl_access/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_bad_sba_tl_access has 1 failures.
0.rv_dm_bad_sba_tl_access.70623964945425686529559667902052699101366119584204412307476724018186073961391
Line 83, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_bad_sba_tl_access/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_autoincr_sba_tl_access has 1 failures.
0.rv_dm_autoincr_sba_tl_access.47051278390909114768333046329553482976982416773751008298518200145769865207872
Line 83, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[NOA] Null object access has 1 failures:
0.rv_dm_tap_fsm.49870920360895893657653400509855983939527640368095062834236186416816900521613
Line 79, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_tap_fsm/latest/run.log
Error-[NOA] Null object access
src/lowrisc_dv_cip_lib_0/seq_lib/cip_base_vseq.sv, 652
The object at dereference depth 0 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@5936) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
0.rv_dm_tap_fsm_rand_reset.55954013973661212734063817825579515389290498417758187570552282190906502618155
Line 76, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 28432717 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@5936) { a_addr: 'h7c46d640 a_data: 'hb5ba979f a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h88 a_opcode: 'h4 a_user: 'h188ef d_param: 'h0 d_source: 'h88 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 28432717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@5826) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
0.rv_dm_stress_all_with_rand_reset.61417332254848406915488155705548899820068829390610031362727578801083931171705
Line 76, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 126866231 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@5826) { a_addr: 'h5f4ac6c0 a_data: 'h2fe13b7 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h4d a_opcode: 'h4 a_user: 'h18af8 d_param: 'h0 d_source: 'h4d d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 126866231 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@6274) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
0.rv_dm_tl_errors.93284903678073971289311554372646854675507148179097153688992000216673518801627
Line 75, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_tl_errors/latest/run.log
UVM_ERROR @ 64937556 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@6274) { a_addr: 'h9f9bf760 a_data: 'h68eb54f1 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hb1 a_opcode: 'h4 a_user: 'h1968a d_param: 'h0 d_source: 'hb1 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 64937556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@6564) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
0.rv_dm_csr_mem_rw_with_rand_reset.25347318994421443403581571975479377276046707373837493096483635263139633352805
Line 76, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 42267514 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@6564) { a_addr: 'h45bbd4e0 a_data: 'h4bfcd915 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h53 a_opcode: 'h4 a_user: 'h182fc d_param: 'h0 d_source: 'h53 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 42267514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---